2017-01-15 17:29:27 +08:00
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; This test ensures that IVUsers works correctly in the legacy pass manager
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; without LCSSA and in the specific ways that some of its users (LSR) require.
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;
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; FIXME: We need some way to match the precision here in the new PM where loop
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; passes *always* work on LCSSA. This should stop using a different set of
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; checks at that point.
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2017-01-18 03:18:12 +08:00
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; RUN: opt < %s -analyze -iv-users | FileCheck %s --check-prefixes=CHECK,CHECK-NO-LCSSA
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2020-07-16 00:34:44 +08:00
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; RUN: opt < %s -disable-output -passes='print<iv-users>' 2>&1 | FileCheck %s
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2009-06-20 01:33:15 +08:00
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2015-03-05 02:43:29 +08:00
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; Provide legal integer types.
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target datalayout = "n8:16:32:64"
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2009-06-20 01:33:15 +08:00
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; The value of %r is dependent on a polynomial iteration expression.
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2013-10-26 05:35:52 +08:00
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;
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; CHECK-LABEL: IV Users for loop %foo.loop
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2017-01-18 03:18:12 +08:00
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; CHECK-NO-LCSSA: {1,+,3,+,2}<%foo.loop>
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2009-06-20 01:33:15 +08:00
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define i64 @foo(i64 %n) {
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entry:
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2013-10-26 05:35:52 +08:00
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br label %foo.loop
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2009-06-20 01:33:15 +08:00
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2013-10-26 05:35:52 +08:00
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foo.loop:
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%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %foo.loop ]
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2009-06-20 01:33:15 +08:00
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%indvar.next = add i64 %indvar, 1
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%c = icmp eq i64 %indvar.next, %n
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2013-10-26 05:35:52 +08:00
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br i1 %c, label %exit, label %foo.loop
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2009-06-20 01:33:15 +08:00
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exit:
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2009-06-20 08:40:56 +08:00
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%r = mul i64 %indvar.next, %indvar.next
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2009-06-20 01:33:15 +08:00
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ret i64 %r
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}
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2013-10-26 05:35:52 +08:00
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Re-enable "[SCEV] Do not fold dominated SCEVUnknown into AddRecExpr start"
The patch rL303730 was reverted because test lsr-expand-quadratic.ll failed on
many non-X86 configs with this patch. The reason of this is that the patch
makes a correctless fix that changes optimizer's behavior for this test.
Without the change, LSR was making an overconfident simplification basing on a
wrong SCEV. Apparently it did not need the IV analysis to do this. With the
change, it chose a different way to simplify (that wasn't so confident), and
this way required the IV analysis. Now, following the right execution path,
LSR tries to make a transformation relying on IV Users analysis. This analysis
is target-dependent due to this code:
// LSR is not APInt clean, do not touch integers bigger than 64-bits.
// Also avoid creating IVs of non-native types. For example, we don't want a
// 64-bit IV in 32-bit code just because the loop has one 64-bit cast.
uint64_t Width = SE->getTypeSizeInBits(I->getType());
if (Width > 64 || !DL.isLegalInteger(Width))
return false;
To make a proper transformation in this test case, the type i32 needs to be
legal for the specified data layout. When the test runs on some non-X86
configuration (e.g. pure ARM 64), opt gets confused by the specified target
and does not use it, rejecting the specified data layout as well. Instead,
it uses some default layout that does not treat i32 as a legal type
(currently the layout that is used when it is not specified does not have
legal types at all). As result, the transformation we expect to happen does
not happen for this test.
This re-enabling patch does not have any source code changes compared to the
original patch rL303730. The only difference is that the failing test is
moved to X86 directory and now has requirement of running on x86 only to comply
with the specified target triple and data layout.
Differential Revision: https://reviews.llvm.org/D33543
llvm-svn: 303971
2017-05-26 14:47:04 +08:00
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; PR15470: LSR miscompile. The test1 function should return '1'.
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; It is valid to fold SCEVUnknown into the recurrence because it
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; was defined before the loop.
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;
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; SCEV does not know how to denormalize chained recurrences, so make
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; sure they aren't marked as post-inc users.
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;
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; CHECK-LABEL: IV Users for loop %test1.loop
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; CHECK-NO-LCSSA: %sext.us = {0,+,(16777216 + (-16777216 * %sub.us))<nuw><nsw>,+,33554432}<%test1.loop> (post-inc with loop %test1.loop) in %f = ashr i32 %sext.us, 24
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define i32 @test1(i1 %cond) {
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entry:
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%sub.us = select i1 %cond, i32 0, i32 0
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br label %test1.loop
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test1.loop:
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%inc1115.us = phi i32 [ 0, %entry ], [ %inc11.us, %test1.loop ]
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%inc11.us = add nsw i32 %inc1115.us, 1
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%cmp.us = icmp slt i32 %inc11.us, 2
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br i1 %cmp.us, label %test1.loop, label %for.end
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for.end:
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%tobool.us = icmp eq i32 %inc1115.us, 0
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%mul.us = shl i32 %inc1115.us, 24
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%sub.cond.us = sub nsw i32 %inc1115.us, %sub.us
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%sext.us = mul i32 %mul.us, %sub.cond.us
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%f = ashr i32 %sext.us, 24
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br label %exit
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exit:
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ret i32 %f
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}
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2013-10-26 05:35:52 +08:00
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; PR15470: LSR miscompile. The test2 function should return '1'.
|
Re-enable "[SCEV] Do not fold dominated SCEVUnknown into AddRecExpr start"
The patch rL303730 was reverted because test lsr-expand-quadratic.ll failed on
many non-X86 configs with this patch. The reason of this is that the patch
makes a correctless fix that changes optimizer's behavior for this test.
Without the change, LSR was making an overconfident simplification basing on a
wrong SCEV. Apparently it did not need the IV analysis to do this. With the
change, it chose a different way to simplify (that wasn't so confident), and
this way required the IV analysis. Now, following the right execution path,
LSR tries to make a transformation relying on IV Users analysis. This analysis
is target-dependent due to this code:
// LSR is not APInt clean, do not touch integers bigger than 64-bits.
// Also avoid creating IVs of non-native types. For example, we don't want a
// 64-bit IV in 32-bit code just because the loop has one 64-bit cast.
uint64_t Width = SE->getTypeSizeInBits(I->getType());
if (Width > 64 || !DL.isLegalInteger(Width))
return false;
To make a proper transformation in this test case, the type i32 needs to be
legal for the specified data layout. When the test runs on some non-X86
configuration (e.g. pure ARM 64), opt gets confused by the specified target
and does not use it, rejecting the specified data layout as well. Instead,
it uses some default layout that does not treat i32 as a legal type
(currently the layout that is used when it is not specified does not have
legal types at all). As result, the transformation we expect to happen does
not happen for this test.
This re-enabling patch does not have any source code changes compared to the
original patch rL303730. The only difference is that the failing test is
moved to X86 directory and now has requirement of running on x86 only to comply
with the specified target triple and data layout.
Differential Revision: https://reviews.llvm.org/D33543
llvm-svn: 303971
2017-05-26 14:47:04 +08:00
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|
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; It is illegal to fold SCEVUnknown (sext.us) into the recurrence
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|
; because it is defined after the loop where this recurrence belongs.
|
2013-10-26 05:35:52 +08:00
|
|
|
;
|
|
|
|
; SCEV does not know how to denormalize chained recurrences, so make
|
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|
|
; sure they aren't marked as post-inc users.
|
|
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|
;
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|
; CHECK-LABEL: IV Users for loop %test2.loop
|
2018-07-14 07:58:46 +08:00
|
|
|
; CHECK-NO-LCSSA: %sub.cond.us = ((-1 * %sub.us)<nuw><nsw> + {0,+,1}<nuw><nsw><%test2.loop>) (post-inc with loop %test2.loop) in %sext.us = mul i32 %mul.us, %sub.cond.us
|
2013-10-26 05:35:52 +08:00
|
|
|
define i32 @test2() {
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entry:
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br label %test2.loop
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test2.loop:
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%inc1115.us = phi i32 [ 0, %entry ], [ %inc11.us, %test2.loop ]
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%inc11.us = add nsw i32 %inc1115.us, 1
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%cmp.us = icmp slt i32 %inc11.us, 2
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br i1 %cmp.us, label %test2.loop, label %for.end
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for.end:
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|
%tobool.us = icmp eq i32 %inc1115.us, 0
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|
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|
%sub.us = select i1 %tobool.us, i32 0, i32 0
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|
%mul.us = shl i32 %inc1115.us, 24
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|
%sub.cond.us = sub nsw i32 %inc1115.us, %sub.us
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|
%sext.us = mul i32 %mul.us, %sub.cond.us
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|
%f = ashr i32 %sext.us, 24
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|
|
|
br label %exit
|
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|
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|
exit:
|
|
|
|
ret i32 %f
|
|
|
|
}
|