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llvm-project/llvm/test/MC/RISCV/rvf-user-csr-names.s

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[RISCV] Support named operands for CSR instructions. Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
2018-10-05 05:50:54 +08:00
# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
# RUN: | llvm-objdump -d -mattr=+f - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
# RUN: | llvm-objdump -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s
#
# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
# RUN: | llvm-objdump -d -mattr=+f - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
# RUN: | llvm-objdump -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s
##################################
# User Floating Pont CSRs
##################################
# fflags
# name
# CHECK-INST: csrrs t1, fflags, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x00]
# CHECK-INST-ALIAS: frflags t1
[RISCV] Allow access to FP CSRs without F extension Summary: Floating-point CSRs should be accessible even when F extension is not enabled. But pseudo instructions that access floating point CSRs still require the F extension. GNU tools already implement this behavior. RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs. Reviewers: asb Reviewed By: asb Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits Differential Revision: https://reviews.llvm.org/D58932 llvm-svn: 355753
2019-03-09 07:01:08 +08:00
# CHECK-INST-ALIAS-NO-F: csrr t1, fflags
[RISCV] Support named operands for CSR instructions. Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
2018-10-05 05:50:54 +08:00
# uimm12
# CHECK-INST: csrrs t2, fflags, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x00]
# CHECK-INST-ALIAS: frflags t2
[RISCV] Allow access to FP CSRs without F extension Summary: Floating-point CSRs should be accessible even when F extension is not enabled. But pseudo instructions that access floating point CSRs still require the F extension. GNU tools already implement this behavior. RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs. Reviewers: asb Reviewed By: asb Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits Differential Revision: https://reviews.llvm.org/D58932 llvm-svn: 355753
2019-03-09 07:01:08 +08:00
# CHECK-INST-ALIAS-NO-F: csrr t2, fflags
[RISCV] Support named operands for CSR instructions. Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
2018-10-05 05:50:54 +08:00
# name
csrrs t1, fflags, zero
# uimm12
csrrs t2, 0x001, zero
# frm
# name
# CHECK-INST: csrrs t1, frm, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x00]
# CHECK-INST-ALIAS: frrm t1
[RISCV] Allow access to FP CSRs without F extension Summary: Floating-point CSRs should be accessible even when F extension is not enabled. But pseudo instructions that access floating point CSRs still require the F extension. GNU tools already implement this behavior. RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs. Reviewers: asb Reviewed By: asb Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits Differential Revision: https://reviews.llvm.org/D58932 llvm-svn: 355753
2019-03-09 07:01:08 +08:00
# CHECK-INST-ALIAS-NO-F: csrr t1, frm
[RISCV] Support named operands for CSR instructions. Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
2018-10-05 05:50:54 +08:00
# uimm12
# CHECK-INST: csrrs t2, frm, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x00]
# CHECK-INST-ALIAS: frrm t2
[RISCV] Allow access to FP CSRs without F extension Summary: Floating-point CSRs should be accessible even when F extension is not enabled. But pseudo instructions that access floating point CSRs still require the F extension. GNU tools already implement this behavior. RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs. Reviewers: asb Reviewed By: asb Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits Differential Revision: https://reviews.llvm.org/D58932 llvm-svn: 355753
2019-03-09 07:01:08 +08:00
# CHECK-INST-ALIAS-NO-F: csrr t2, frm
[RISCV] Support named operands for CSR instructions. Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
2018-10-05 05:50:54 +08:00
# name
csrrs t1, frm, zero
# uimm12
csrrs t2, 0x002, zero
# fcsr
# name
# CHECK-INST: csrrs t1, fcsr, zero
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x00]
# CHECK-INST-ALIAS: frcsr t1
[RISCV] Allow access to FP CSRs without F extension Summary: Floating-point CSRs should be accessible even when F extension is not enabled. But pseudo instructions that access floating point CSRs still require the F extension. GNU tools already implement this behavior. RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs. Reviewers: asb Reviewed By: asb Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits Differential Revision: https://reviews.llvm.org/D58932 llvm-svn: 355753
2019-03-09 07:01:08 +08:00
# CHECK-INST-ALIAS-NO-F: csrr t1, fcsr
[RISCV] Support named operands for CSR instructions. Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
2018-10-05 05:50:54 +08:00
# uimm12
# CHECK-INST: csrrs t2, fcsr, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x00]
# CHECK-INST-ALIAS: frcsr t2
[RISCV] Allow access to FP CSRs without F extension Summary: Floating-point CSRs should be accessible even when F extension is not enabled. But pseudo instructions that access floating point CSRs still require the F extension. GNU tools already implement this behavior. RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs. Reviewers: asb Reviewed By: asb Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits Differential Revision: https://reviews.llvm.org/D58932 llvm-svn: 355753
2019-03-09 07:01:08 +08:00
# CHECK-INST-ALIAS-NO-F: csrr t2, fcsr
[RISCV] Support named operands for CSR instructions. Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
2018-10-05 05:50:54 +08:00
# name
csrrs t1, fcsr, zero
# uimm12
csrrs t2, 0x003, zero