[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
|
|
# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding < %s \
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|
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
|
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|
# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \
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|
# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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|
# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
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|
# RUN: | llvm-objdump -triple riscv32 -mattr=+c -d - \
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|
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
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|
# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
|
[RISCV] Support llvm-objdump -M no-aliases and -M numeric
Summary:
Now that llvm-objdump allows target-specific options, we match the
`no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump.
This is done by overriding the variables used for the command-line options, so
that the command-line options are still supported.
This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use
`llvm-objdump -M no-aliases`.
Reviewers: luismarques, asb
Reviewed By: luismarques, asb
Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66139
llvm-svn: 371534
2019-09-11 00:24:03 +08:00
|
|
|
# RUN: | llvm-objdump -triple riscv32 -mattr=+c -d -M no-aliases - \
|
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
|
|
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
|
|
|
|
|
|
|
|
|
|
# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \
|
|
|
|
|
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
|
|
|
|
|
# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \
|
|
|
|
|
# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
|
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|
|
|
# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
|
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|
|
|
# RUN: | llvm-objdump -triple riscv64 -mattr=+c -d - \
|
|
|
|
|
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
|
|
|
|
|
# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
|
[RISCV] Support llvm-objdump -M no-aliases and -M numeric
Summary:
Now that llvm-objdump allows target-specific options, we match the
`no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump.
This is done by overriding the variables used for the command-line options, so
that the command-line options are still supported.
This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use
`llvm-objdump -M no-aliases`.
Reviewers: luismarques, asb
Reviewed By: luismarques, asb
Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66139
llvm-svn: 371534
2019-09-11 00:24:03 +08:00
|
|
|
# RUN: | llvm-objdump -triple riscv64 -mattr=+c -d -M no-aliases - \
|
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
|
|
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
|
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|
[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
Summary:
GCC compresses the pseudo instruction "mv rd, rs", which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".
In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.
In this patch we fix that by adding an addi to c.mv compression pattern, the
instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
gcc does.
Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).
Reviewers: asb, apazos, zzheng, mgrang, shiva0217
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D45583
llvm-svn: 329939
2018-04-13 03:22:40 +08:00
|
|
|
# CHECK-BYTES: 2e 85
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|
|
# CHECK-ALIAS: add a0, zero, a1
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|
# CHECK-INST: c.mv a0, a1
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|
# CHECK: # encoding: [0x2e,0x85]
|
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|
|
addi a0, a1, 0
|
|
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|
|
|
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
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|
# CHECK-BYTES: e0 1f
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|
# CHECK-ALIAS: addi s0, sp, 1020
|
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|
# CHECK-INST: c.addi4spn s0, sp, 1020
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|
# CHECK: # encoding: [0xe0,0x1f]
|
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|
|
addi s0, sp, 1020
|
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|
# CHECK-BYTES: e0 5f
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|
# CHECK-ALIAS: lw s0, 124(a5)
|
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|
# CHECK-INST: c.lw s0, 124(a5)
|
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|
# CHECK: # encoding: [0xe0,0x5f]
|
|
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|
|
lw s0, 124(a5)
|
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|
# CHECK-BYTES: e0 df
|
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|
# CHECK-ALIAS: sw s0, 124(a5)
|
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|
|
# CHECK-INST: c.sw s0, 124(a5)
|
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|
# CHECK: # encoding: [0xe0,0xdf]
|
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|
|
|
sw s0, 124(a5)
|
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|
# CHECK-BYTES: 01 00
|
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|
# CHECK-ALIAS: nop
|
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|
|
# CHECK-INST: c.nop
|
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|
# CHECK: # encoding: [0x01,0x00]
|
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|
|
nop
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|
# CHECK-BYTES: 81 10
|
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|
# CHECK-ALIAS: addi ra, ra, -32
|
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|
# CHECK-INST: c.addi ra, -32
|
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|
# CHECK: # encoding: [0x81,0x10]
|
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|
addi ra, ra, -32
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# CHECK-BYTES: 85 50
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# CHECK-ALIAS: addi ra, zero, -31
|
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# CHECK-INST: c.li ra, -31
|
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|
# CHECK: # encoding: [0x85,0x50]
|
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|
addi ra, zero, -31
|
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# CHECK-BYTES: 39 71
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# CHECK-ALIAS: addi sp, sp, -64
|
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# CHECK-INST: c.addi16sp sp, -64
|
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|
# CHECK: # encoding: [0x39,0x71]
|
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|
|
addi sp, sp, -64
|
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# CHECK-BYTES: fd 61
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# CHECK-ALIAS: lui gp, 31
|
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# CHECK-INST: c.lui gp, 31
|
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# CHECK: # encoding: [0xfd,0x61]
|
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|
lui gp, 31
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# CHECK-BYTES: 7d 80
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# CHECK-ALIAS: srli s0, s0, 31
|
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|
# CHECK-INST: c.srli s0, 31
|
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|
# CHECK: # encoding: [0x7d,0x80]
|
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|
srli s0, s0, 31
|
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# CHECK-BYTES: 7d 84
|
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# CHECK-ALIAS: srai s0, s0, 31
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# CHECK-INST: c.srai s0, 31
|
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|
# CHECK: # encoding: [0x7d,0x84]
|
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|
srai s0, s0, 31
|
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# CHECK-BYTES: 7d 88
|
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# CHECK-ALIAS: andi s0, s0, 31
|
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|
# CHECK-INST: c.andi s0, 31
|
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|
# CHECK: # encoding: [0x7d,0x88]
|
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|
|
andi s0, s0, 31
|
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# CHECK-BYTES: 1d 8c
|
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# CHECK-ALIAS: sub s0, s0, a5
|
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# CHECK-INST: c.sub s0, a5
|
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|
# CHECK: # encoding: [0x1d,0x8c]
|
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|
|
sub s0, s0, a5
|
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|
# CHECK-BYTES: 3d 8c
|
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|
# CHECK-ALIAS: xor s0, s0, a5
|
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|
# CHECK-INST: c.xor s0, a5
|
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|
# CHECK: # encoding: [0x3d,0x8c]
|
|
|
|
|
xor s0, s0, a5
|
|
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|
|
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|
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|
# CHECK-BYTES: 3d 8c
|
|
|
|
|
# CHECK-ALIAS: xor s0, s0, a5
|
|
|
|
|
# CHECK-INST: c.xor s0, a5
|
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|
|
# CHECK: # encoding: [0x3d,0x8c]
|
|
|
|
|
xor s0, a5, s0
|
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|
# CHECK-BYTES: 5d 8c
|
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|
# CHECK-ALIAS: or s0, s0, a5
|
|
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|
# CHECK-INST: c.or s0, a5
|
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|
# CHECK: # encoding: [0x5d,0x8c]
|
|
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|
|
or s0, s0, a5
|
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# CHECK-BYTES: 45 8c
|
|
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|
|
# CHECK-ALIAS: or s0, s0, s1
|
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|
# CHECK-INST: c.or s0, s1
|
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|
|
# CHECK: # encoding: [0x45,0x8c]
|
|
|
|
|
or s0, s1, s0
|
|
|
|
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|
# CHECK-BYTES: 7d 8c
|
|
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|
# CHECK-ALIAS: and s0, s0, a5
|
|
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|
# CHECK-INST: c.and s0, a5
|
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|
# CHECK: # encoding: [0x7d,0x8c]
|
|
|
|
|
and s0, s0, a5
|
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|
|
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|
# CHECK-BYTES: 7d 8c
|
|
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|
|
# CHECK-ALIAS: and s0, s0, a5
|
|
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|
|
# CHECK-INST: c.and s0, a5
|
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|
|
# CHECK: # encoding: [0x7d,0x8c]
|
|
|
|
|
and s0, a5, s0
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 01 b0
|
|
|
|
|
# CHECK-ALIAS: j -2048
|
|
|
|
|
# CHECK-INST: c.j -2048
|
|
|
|
|
# CHECK: # encoding: [0x01,0xb0]
|
|
|
|
|
jal zero, -2048
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 01 d0
|
|
|
|
|
# CHECK-ALIAS: beqz s0, -256
|
|
|
|
|
# CHECK-INST: c.beqz s0, -256
|
|
|
|
|
# CHECK: # encoding: [0x01,0xd0]
|
|
|
|
|
beq s0, zero, -256
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 7d ec
|
|
|
|
|
# CHECk-ALIAS: bnez s0, 254
|
|
|
|
|
# CHECK-INST: c.bnez s0, 254
|
|
|
|
|
# CHECK: # encoding: [0x7d,0xec]
|
|
|
|
|
bne s0, zero, 254
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 7e 04
|
|
|
|
|
# CHECK-ALIAS: slli s0, s0, 31
|
|
|
|
|
# CHECK-INST: c.slli s0, 31
|
|
|
|
|
# CHECK: # encoding: [0x7e,0x04]
|
|
|
|
|
slli s0, s0, 31
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: fe 50
|
|
|
|
|
# CHECK-ALIAS: lw ra, 252(sp)
|
|
|
|
|
# CHECK-INST: c.lwsp ra, 252(sp)
|
|
|
|
|
# CHECK: # encoding: [0xfe,0x50]
|
|
|
|
|
lw ra, 252(sp)
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 82 80
|
|
|
|
|
# CHECK-ALIAS: ret
|
|
|
|
|
# CHECK-INST: c.jr ra
|
|
|
|
|
# CHECK: # encoding: [0x82,0x80]
|
2019-07-16 12:56:43 +08:00
|
|
|
jalr zero, 0(ra)
|
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
|
|
|
|
|
|
|
# CHECK-BYTES: 92 80
|
|
|
|
|
# CHECK-ALIAS: add ra, zero, tp
|
|
|
|
|
# CHECK-INST: c.mv ra, tp
|
|
|
|
|
# CHECK: # encoding: [0x92,0x80]
|
|
|
|
|
add ra, zero, tp
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 92 80
|
|
|
|
|
# CHECK-ALIAS: add ra, zero, tp
|
|
|
|
|
# CHECK-INST: c.mv ra, tp
|
|
|
|
|
# CHECK: # encoding: [0x92,0x80]
|
|
|
|
|
add ra, tp, zero
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 02 90
|
|
|
|
|
# CHECK-ALIAS: ebreak
|
|
|
|
|
# CHECK-INST: c.ebreak
|
|
|
|
|
# CHECK: # encoding: [0x02,0x90]
|
|
|
|
|
ebreak
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 02 94
|
|
|
|
|
# CHECK-ALIAS: jalr s0
|
|
|
|
|
# CHECK-INST: c.jalr s0
|
|
|
|
|
# CHECK: # encoding: [0x02,0x94]
|
2019-07-16 12:56:43 +08:00
|
|
|
jalr ra, 0(s0)
|
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
|
|
|
|
|
|
|
|
# CHECK-BYTES: 3e 94
|
|
|
|
|
# CHECK-ALIAS: add s0, s0, a5
|
|
|
|
|
# CHECK-INST: c.add s0, a5
|
|
|
|
|
# CHECK: # encoding: [0x3e,0x94]
|
|
|
|
|
add s0, a5, s0
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 3e 94
|
|
|
|
|
# CHECK-ALIAS: add s0, s0, a5
|
|
|
|
|
# CHECK-INST: c.add s0, a5
|
|
|
|
|
# CHECK: # encoding: [0x3e,0x94]
|
|
|
|
|
add s0, s0, a5
|
|
|
|
|
|
|
|
|
|
# CHECK-BYTES: 82 df
|
|
|
|
|
# CHECK-ALIAS: sw zero, 252(sp)
|
|
|
|
|
# CHECK-INST: c.swsp zero, 252(sp)
|
|
|
|
|
# CHECK: # encoding: [0x82,0xdf]
|
|
|
|
|
sw zero, 252(sp)
|
2018-11-30 21:39:17 +08:00
|
|
|
|
|
|
|
|
# CHECK-BYTES: 00 00
|
|
|
|
|
# CHECK-ALIAS: unimp
|
|
|
|
|
# CHECK-INST: c.unimp
|
|
|
|
|
# CHECK: # encoding: [0x00,0x00]
|
|
|
|
|
unimp
|