2016-10-20 16:27:16 +08:00
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//==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Scheduler resources
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2018-07-20 17:40:43 +08:00
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// These resources are used to express decoder grouping rules. The number of
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// decoder slots needed by an instructions is normally one, but there are
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// exceptions.
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def NormalGr : SchedWrite;
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def Cracked : SchedWrite;
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2016-10-20 16:27:16 +08:00
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def GroupAlone : SchedWrite;
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def BeginGroup : SchedWrite;
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def EndGroup : SchedWrite;
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2018-07-20 17:40:43 +08:00
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// A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
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def LSULatency : SchedWrite;
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2016-10-20 16:27:16 +08:00
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2018-07-20 17:40:43 +08:00
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// Operand WriteLatencies.
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def WLat1 : SchedWrite;
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def WLat2 : SchedWrite;
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def WLat3 : SchedWrite;
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def WLat4 : SchedWrite;
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def WLat5 : SchedWrite;
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def WLat6 : SchedWrite;
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def WLat7 : SchedWrite;
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def WLat8 : SchedWrite;
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def WLat9 : SchedWrite;
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def WLat10 : SchedWrite;
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def WLat11 : SchedWrite;
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def WLat12 : SchedWrite;
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def WLat15 : SchedWrite;
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def WLat16 : SchedWrite;
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def WLat20 : SchedWrite;
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def WLat26 : SchedWrite;
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def WLat30 : SchedWrite;
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def WLat1LSU : WriteSequence<[WLat1, LSULatency]>;
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def WLat2LSU : WriteSequence<[WLat2, LSULatency]>;
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def WLat3LSU : WriteSequence<[WLat3, LSULatency]>;
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def WLat4LSU : WriteSequence<[WLat4, LSULatency]>;
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def WLat6LSU : WriteSequence<[WLat6, LSULatency]>;
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def WLat5LSU : WriteSequence<[WLat5, LSULatency]>;
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def WLat7LSU : WriteSequence<[WLat7, LSULatency]>;
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def WLat8LSU : WriteSequence<[WLat8, LSULatency]>;
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def WLat11LSU : WriteSequence<[WLat11, LSULatency]>;
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def WLat16LSU : WriteSequence<[WLat16, LSULatency]>;
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// ReadAdvances, used for the register operand next to a memory operand,
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// modelling that the register operand is needed later than the address
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// operands.
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def RegReadAdv : SchedRead;
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// Fixed-point units
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def FXa : SchedWrite;
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def FXa2 : SchedWrite;
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def FXa3 : SchedWrite;
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def FXa4 : SchedWrite;
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def FXb : SchedWrite;
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def FXb2 : SchedWrite;
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def FXb3 : SchedWrite;
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def FXb4 : SchedWrite;
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def FXb5 : SchedWrite;
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def FXU : SchedWrite;
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def FXU2 : SchedWrite;
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def FXU3 : SchedWrite;
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def FXU4 : SchedWrite;
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def FXU5 : SchedWrite;
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def FXU6 : SchedWrite;
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// Load/store unit
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def LSU : SchedWrite;
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def LSU2 : SchedWrite;
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def LSU3 : SchedWrite;
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def LSU4 : SchedWrite;
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def LSU5 : SchedWrite;
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// Floating point unit (zEC12 and earlier)
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def FPU : SchedWrite;
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def FPU2 : SchedWrite;
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def FPU4 : SchedWrite;
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2017-05-10 20:42:45 +08:00
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def DFU : SchedWrite;
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def DFU2 : SchedWrite;
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def DFU4 : SchedWrite;
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2016-10-20 16:27:16 +08:00
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2017-07-18 01:41:11 +08:00
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// Vector sub units (z13 and later)
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def VecBF : SchedWrite;
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def VecBF2 : SchedWrite;
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def VecBF4 : SchedWrite;
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def VecDF : SchedWrite;
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def VecDF2 : SchedWrite;
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def VecDF4 : SchedWrite;
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2017-05-10 20:42:45 +08:00
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def VecDFX : SchedWrite;
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def VecDFX2 : SchedWrite;
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def VecDFX4 : SchedWrite;
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def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit.
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def VecMul : SchedWrite;
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def VecStr : SchedWrite;
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def VecXsPm : SchedWrite;
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def VecXsPm2 : SchedWrite;
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// Virtual branching unit
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def VBU : SchedWrite;
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2018-07-20 17:40:43 +08:00
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// Millicode
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def MCD : SchedWrite;
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2016-10-20 16:27:16 +08:00
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2017-07-18 01:41:11 +08:00
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include "SystemZScheduleZ14.td"
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2016-10-20 16:27:16 +08:00
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include "SystemZScheduleZ13.td"
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include "SystemZScheduleZEC12.td"
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include "SystemZScheduleZ196.td"
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