2014-05-01 05:34:11 +08:00
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//===-- llvm/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "DbgValueHistoryCalculator.h"
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2014-10-06 23:31:04 +08:00
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#include "llvm/ADT/BitVector.h"
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2014-05-21 02:34:54 +08:00
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#include "llvm/ADT/SmallVector.h"
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2014-05-01 05:34:11 +08:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2014-08-02 06:11:58 +08:00
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#include "llvm/IR/DebugInfo.h"
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2014-05-01 05:34:11 +08:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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2014-05-21 02:34:54 +08:00
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#include <algorithm>
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#include <map>
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2014-10-06 23:31:04 +08:00
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using namespace llvm;
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2014-05-01 05:34:11 +08:00
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#define DEBUG_TYPE "dwarfdebug"
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2014-05-21 02:34:54 +08:00
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// \brief If @MI is a DBG_VALUE with debug value described by a
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// defined register, returns the number of this register.
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// In the other case, returns 0.
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static unsigned isDescribedByReg(const MachineInstr &MI) {
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assert(MI.isDebugValue());
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Move the complex address expression out of DIVariable and into an extra
argument of the llvm.dbg.declare/llvm.dbg.value intrinsics.
Previously, DIVariable was a variable-length field that has an optional
reference to a Metadata array consisting of a variable number of
complex address expressions. In the case of OpPiece expressions this is
wasting a lot of storage in IR, because when an aggregate type is, e.g.,
SROA'd into all of its n individual members, the IR will contain n copies
of the DIVariable, all alike, only differing in the complex address
reference at the end.
By making the complex address into an extra argument of the
dbg.value/dbg.declare intrinsics, all of the pieces can reference the
same variable and the complex address expressions can be uniqued across
the CU, too.
Down the road, this will allow us to move other flags, such as
"indirection" out of the DIVariable, too.
The new intrinsics look like this:
declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr)
declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr)
This patch adds a new LLVM-local tag to DIExpressions, so we can detect
and pretty-print DIExpression metadata nodes.
What this patch doesn't do:
This patch does not touch the "Indirect" field in DIVariable; but moving
that into the expression would be a natural next step.
http://reviews.llvm.org/D4919
rdar://problem/17994491
Thanks to dblaikie and dexonsmith for reviewing this patch!
Note: I accidentally committed a bogus older version of this patch previously.
llvm-svn: 218787
2014-10-02 02:55:02 +08:00
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assert(MI.getNumOperands() == 4);
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2014-05-21 02:34:54 +08:00
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// If location of variable is described using a register (directly or
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// indirecltly), this register is always a first operand.
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return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
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}
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2014-05-28 07:09:50 +08:00
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void DbgValueHistoryMap::startInstrRange(const MDNode *Var,
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const MachineInstr &MI) {
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// Instruction range should start with a DBG_VALUE instruction for the
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// variable.
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Move the complex address expression out of DIVariable and into an extra
argument of the llvm.dbg.declare/llvm.dbg.value intrinsics.
Previously, DIVariable was a variable-length field that has an optional
reference to a Metadata array consisting of a variable number of
complex address expressions. In the case of OpPiece expressions this is
wasting a lot of storage in IR, because when an aggregate type is, e.g.,
SROA'd into all of its n individual members, the IR will contain n copies
of the DIVariable, all alike, only differing in the complex address
reference at the end.
By making the complex address into an extra argument of the
dbg.value/dbg.declare intrinsics, all of the pieces can reference the
same variable and the complex address expressions can be uniqued across
the CU, too.
Down the road, this will allow us to move other flags, such as
"indirection" out of the DIVariable, too.
The new intrinsics look like this:
declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr)
declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr)
This patch adds a new LLVM-local tag to DIExpressions, so we can detect
and pretty-print DIExpression metadata nodes.
What this patch doesn't do:
This patch does not touch the "Indirect" field in DIVariable; but moving
that into the expression would be a natural next step.
http://reviews.llvm.org/D4919
rdar://problem/17994491
Thanks to dblaikie and dexonsmith for reviewing this patch!
Note: I accidentally committed a bogus older version of this patch previously.
llvm-svn: 218787
2014-10-02 02:55:02 +08:00
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assert(MI.isDebugValue() && "not a DBG_VALUE");
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2014-05-28 07:09:50 +08:00
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auto &Ranges = VarInstrRanges[Var];
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if (!Ranges.empty() && Ranges.back().second == nullptr &&
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Ranges.back().first->isIdenticalTo(&MI)) {
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DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n"
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<< "\t" << Ranges.back().first << "\t" << MI << "\n");
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return;
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}
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Ranges.push_back(std::make_pair(&MI, nullptr));
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}
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void DbgValueHistoryMap::endInstrRange(const MDNode *Var,
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const MachineInstr &MI) {
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auto &Ranges = VarInstrRanges[Var];
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// Verify that the current instruction range is not yet closed.
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assert(!Ranges.empty() && Ranges.back().second == nullptr);
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// For now, instruction ranges are not allowed to cross basic block
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// boundaries.
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assert(Ranges.back().first->getParent() == MI.getParent());
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Ranges.back().second = &MI;
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}
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unsigned DbgValueHistoryMap::getRegisterForVar(const MDNode *Var) const {
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const auto &I = VarInstrRanges.find(Var);
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if (I == VarInstrRanges.end())
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return 0;
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const auto &Ranges = I->second;
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if (Ranges.empty() || Ranges.back().second != nullptr)
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return 0;
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return isDescribedByReg(*Ranges.back().first);
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}
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namespace {
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// Maps physreg numbers to the variables they describe.
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typedef std::map<unsigned, SmallVector<const MDNode *, 1>> RegDescribedVarsMap;
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}
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2014-05-21 02:34:54 +08:00
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// \brief Claim that @Var is not described by @RegNo anymore.
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static void dropRegDescribedVar(RegDescribedVarsMap &RegVars,
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unsigned RegNo, const MDNode *Var) {
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const auto &I = RegVars.find(RegNo);
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assert(RegNo != 0U && I != RegVars.end());
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auto &VarSet = I->second;
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const auto &VarPos = std::find(VarSet.begin(), VarSet.end(), Var);
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assert(VarPos != VarSet.end());
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VarSet.erase(VarPos);
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// Don't keep empty sets in a map to keep it as small as possible.
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if (VarSet.empty())
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RegVars.erase(I);
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}
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// \brief Claim that @Var is now described by @RegNo.
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static void addRegDescribedVar(RegDescribedVarsMap &RegVars,
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unsigned RegNo, const MDNode *Var) {
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assert(RegNo != 0U);
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2014-05-28 07:09:50 +08:00
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auto &VarSet = RegVars[RegNo];
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assert(std::find(VarSet.begin(), VarSet.end(), Var) == VarSet.end());
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VarSet.push_back(Var);
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2014-05-21 02:34:54 +08:00
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}
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2014-10-06 23:31:04 +08:00
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// \brief Terminate the location range for variables described by register at
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// @I by inserting @ClobberingInstr to their history.
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static void clobberRegisterUses(RegDescribedVarsMap &RegVars,
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RegDescribedVarsMap::iterator I,
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DbgValueHistoryMap &HistMap,
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const MachineInstr &ClobberingInstr) {
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// Iterate over all variables described by this register and add this
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// instruction to their history, clobbering it.
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for (const auto &Var : I->second)
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HistMap.endInstrRange(Var, ClobberingInstr);
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RegVars.erase(I);
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}
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2014-05-21 02:34:54 +08:00
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// \brief Terminate the location range for variables described by register
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// @RegNo by inserting @ClobberingInstr to their history.
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static void clobberRegisterUses(RegDescribedVarsMap &RegVars, unsigned RegNo,
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DbgValueHistoryMap &HistMap,
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const MachineInstr &ClobberingInstr) {
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const auto &I = RegVars.find(RegNo);
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if (I == RegVars.end())
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return;
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2014-10-06 23:31:04 +08:00
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clobberRegisterUses(RegVars, I, HistMap, ClobberingInstr);
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2014-05-21 02:34:54 +08:00
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}
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2014-08-07 02:41:24 +08:00
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// \brief Collect all registers clobbered by @MI and apply the functor
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// @Func to their RegNo.
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// @Func should be a functor with a void(unsigned) signature. We're
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// not using std::function here for performance reasons. It has a
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// small but measurable impact. By using a functor instead of a
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// std::set& here, we can avoid the overhead of constructing
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// temporaries in calculateDbgValueHistory, which has a significant
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// performance impact.
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template<typename Callable>
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static void applyToClobberedRegisters(const MachineInstr &MI,
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2014-06-10 05:53:47 +08:00
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const TargetRegisterInfo *TRI,
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2014-08-07 02:41:24 +08:00
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Callable Func) {
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2014-05-21 02:34:54 +08:00
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isDef() || !MO.getReg())
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continue;
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2014-06-10 05:53:47 +08:00
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for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
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2014-08-07 02:41:24 +08:00
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Func(*AI);
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2014-05-21 02:34:54 +08:00
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}
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}
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2014-06-10 05:53:47 +08:00
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// \brief Returns the first instruction in @MBB which corresponds to
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// the function epilogue, or nullptr if @MBB doesn't contain an epilogue.
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static const MachineInstr *getFirstEpilogueInst(const MachineBasicBlock &MBB) {
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auto LastMI = MBB.getLastNonDebugInstr();
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if (LastMI == MBB.end() || !LastMI->isReturn())
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return nullptr;
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// Assume that epilogue starts with instruction having the same debug location
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// as the return instruction.
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DebugLoc LastLoc = LastMI->getDebugLoc();
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auto Res = LastMI;
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2014-10-06 23:31:04 +08:00
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for (MachineBasicBlock::const_reverse_iterator I(std::next(LastMI)),
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E = MBB.rend();
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I != E; ++I) {
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2014-06-10 05:53:47 +08:00
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if (I->getDebugLoc() != LastLoc)
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return Res;
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2014-10-06 23:31:04 +08:00
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Res = &*I;
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2014-06-10 05:53:47 +08:00
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}
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// If all instructions have the same debug location, assume whole MBB is
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// an epilogue.
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return MBB.begin();
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}
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// \brief Collect registers that are modified in the function body (their
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2014-08-07 02:41:24 +08:00
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// contents is changed outside of the prologue and epilogue).
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2014-06-10 05:53:47 +08:00
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static void collectChangingRegs(const MachineFunction *MF,
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const TargetRegisterInfo *TRI,
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2014-10-06 23:31:04 +08:00
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BitVector &Regs) {
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2014-06-10 05:53:47 +08:00
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for (const auto &MBB : *MF) {
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auto FirstEpilogueInst = getFirstEpilogueInst(MBB);
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2014-08-07 02:41:19 +08:00
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2014-06-10 05:53:47 +08:00
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for (const auto &MI : MBB) {
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2014-08-07 02:41:19 +08:00
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if (&MI == FirstEpilogueInst)
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break;
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if (!MI.getFlag(MachineInstr::FrameSetup))
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2014-10-06 23:31:04 +08:00
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applyToClobberedRegisters(MI, TRI, [&](unsigned r) { Regs.set(r); });
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2014-06-10 05:53:47 +08:00
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}
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}
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2014-05-21 02:34:54 +08:00
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}
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2014-10-06 23:31:04 +08:00
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void llvm::calculateDbgValueHistory(const MachineFunction *MF,
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const TargetRegisterInfo *TRI,
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DbgValueHistoryMap &Result) {
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BitVector ChangingRegs(TRI->getNumRegs());
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2014-06-10 05:53:47 +08:00
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collectChangingRegs(MF, TRI, ChangingRegs);
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2014-05-21 02:34:54 +08:00
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2014-06-10 05:53:47 +08:00
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RegDescribedVarsMap RegVars;
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2014-05-21 02:34:54 +08:00
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for (const auto &MBB : *MF) {
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for (const auto &MI : MBB) {
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if (!MI.isDebugValue()) {
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// Not a DBG_VALUE instruction. It may clobber registers which describe
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// some variables.
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2014-08-07 02:41:24 +08:00
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applyToClobberedRegisters(MI, TRI, [&](unsigned RegNo) {
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2014-10-06 23:31:04 +08:00
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if (ChangingRegs.test(RegNo))
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2014-06-10 05:53:47 +08:00
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clobberRegisterUses(RegVars, RegNo, Result, MI);
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2014-08-07 02:41:24 +08:00
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});
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2014-05-21 02:34:54 +08:00
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continue;
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2014-05-01 05:34:11 +08:00
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}
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2014-05-28 06:35:00 +08:00
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assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!");
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2014-08-02 06:11:58 +08:00
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// Use the base variable (without any DW_OP_piece expressions)
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// as index into History. The full variables including the
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// piece expressions are attached to the MI.
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Move the complex address expression out of DIVariable and into an extra
argument of the llvm.dbg.declare/llvm.dbg.value intrinsics.
Previously, DIVariable was a variable-length field that has an optional
reference to a Metadata array consisting of a variable number of
complex address expressions. In the case of OpPiece expressions this is
wasting a lot of storage in IR, because when an aggregate type is, e.g.,
SROA'd into all of its n individual members, the IR will contain n copies
of the DIVariable, all alike, only differing in the complex address
reference at the end.
By making the complex address into an extra argument of the
dbg.value/dbg.declare intrinsics, all of the pieces can reference the
same variable and the complex address expressions can be uniqued across
the CU, too.
Down the road, this will allow us to move other flags, such as
"indirection" out of the DIVariable, too.
The new intrinsics look like this:
declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr)
declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr)
This patch adds a new LLVM-local tag to DIExpressions, so we can detect
and pretty-print DIExpression metadata nodes.
What this patch doesn't do:
This patch does not touch the "Indirect" field in DIVariable; but moving
that into the expression would be a natural next step.
http://reviews.llvm.org/D4919
rdar://problem/17994491
Thanks to dblaikie and dexonsmith for reviewing this patch!
Note: I accidentally committed a bogus older version of this patch previously.
llvm-svn: 218787
2014-10-02 02:55:02 +08:00
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DIVariable Var = MI.getDebugVariable();
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2014-05-01 05:34:11 +08:00
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2014-05-28 07:09:50 +08:00
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if (unsigned PrevReg = Result.getRegisterForVar(Var))
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dropRegDescribedVar(RegVars, PrevReg, Var);
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Result.startInstrRange(Var, MI);
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2014-05-21 02:34:54 +08:00
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2014-05-28 07:09:50 +08:00
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if (unsigned NewReg = isDescribedByReg(MI))
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addRegDescribedVar(RegVars, NewReg, Var);
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2014-05-01 05:34:11 +08:00
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}
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2014-05-21 02:34:54 +08:00
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// Make sure locations for register-described variables are valid only
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// until the end of the basic block (unless it's the last basic block, in
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// which case let their liveness run off to the end of the function).
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2014-10-06 23:31:04 +08:00
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if (!MBB.empty() && &MBB != &MF->back()) {
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for (auto I = RegVars.begin(), E = RegVars.end(); I != E;) {
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auto CurElem = I++; // CurElem can be erased below.
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if (ChangingRegs.test(CurElem->first))
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clobberRegisterUses(RegVars, CurElem, Result, MBB.back());
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}
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2014-06-10 05:53:47 +08:00
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}
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2014-05-01 05:34:11 +08:00
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}
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}
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