llvm-project/llvm/test/CodeGen/AArch64/machine-scheduler.mir

# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler  -verify-machineinstrs  -o - %s | FileCheck %s

--- |
  define i64 @load_imp-def(i64* nocapture %P, i32 %v) {
  entry:
    %0 = bitcast i64* %P to i32*
    %1 = load i32, i32* %0
    %conv = zext i32 %1 to i64
    %arrayidx19 = getelementptr inbounds i64, i64* %P, i64 1
    %arrayidx1 = bitcast i64* %arrayidx19 to i32*
    store i32 %v, i32* %arrayidx1
    %2 = load i64, i64* %arrayidx19
    %and = and i64 %2, 4294967295
    %add = add nuw nsw i64 %and, %conv
    ret i64 %add
  }
...
---
# CHECK-LABEL: name: load_imp-def
# CHECK: bb.0.entry:
# CHECK: LDRWui %x0, 0
# CHECK: LDRWui %x0, 1
# CHECK: STRWui %w1, %x0, 2
name: load_imp-def
tracksRegLiveness: true
body: |
  bb.0.entry:
    liveins: %w1, %x0
    %w8 = LDRWui %x0, 1, implicit-def %x8  :: (load 4 from %ir.0)
    STRWui killed %w1, %x0, 2 :: (store 4 into %ir.arrayidx1)
    %w9 = LDRWui killed %x0, 0, implicit-def %x9  :: (load 4 from %ir.arrayidx19, align 8)
    %x0 = ADDXrr killed %x9, killed %x8
    RET_ReallyLR implicit %x0
...