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llvm-project/llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td

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Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
//===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the G4+ (7450) processor.
//
//===----------------------------------------------------------------------===//
Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
2010-04-19 04:31:01 +08:00
def IU3 : FuncUnit; // integer unit 3 (7450 simple)
def IU4 : FuncUnit; // integer unit 4 (7450 simple)
def G4PlusItineraries : ProcessorItineraries<
Add support to model pipeline bypass / forwarding. llvm-svn: 115005
2010-09-29 07:50:49 +08:00
[IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
InstrItinData<LdStGeneral , [InstrStage<3, [SLU]>]>,
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>,
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>,
InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>,
InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>,
InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>,
InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>,
InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>,
InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>,
InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>,
InstrItinData<VecVSR , [InstrStage<2, [VPU]>]>
]>;