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llvm-project/llvm/test/MC/AMDGPU/vop2-err.s

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R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
AMDGPU: Remove -mcpu=SI Leftover from before amdgcn/r600 split. llvm-svn: 310277
2017-08-08 02:30:35 +08:00
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
//===----------------------------------------------------------------------===//
// Generic checks
//===----------------------------------------------------------------------===//
v_mul_i32_i24 v1, v2, 100
// CHECK: error: invalid operand for instruction
[AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC. Another step for unification llvm assembler/disassembler with sp3. Besides, CodeGen output is a bit improved, thus changes in CodeGen tests. Assembler/Disassembler tests updated/added. Differential Revision: http://reviews.llvm.org/D20796 llvm-svn: 271900
2016-06-06 23:23:43 +08:00
v_cndmask_b32 v1, v2, v3
// CHECK: error: too few operands for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
//===----------------------------------------------------------------------===//
// _e32 checks
//===----------------------------------------------------------------------===//
// Immediate src1
v_mul_i32_i24_e32 v1, v2, 100
// CHECK: error: invalid operand for instruction
// sgpr src1
v_mul_i32_i24_e32 v1, v2, s3
// CHECK: error: invalid operand for instruction
[AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC. Another step for unification llvm assembler/disassembler with sp3. Besides, CodeGen output is a bit improved, thus changes in CodeGen tests. Assembler/Disassembler tests updated/added. Differential Revision: http://reviews.llvm.org/D20796 llvm-svn: 271900
2016-06-06 23:23:43 +08:00
v_cndmask_b32_e32 v1, v2, v3, s[0:1]
// CHECK: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
//===----------------------------------------------------------------------===//
// _e64 checks
//===----------------------------------------------------------------------===//
// Immediate src0
v_mul_i32_i24_e64 v1, 100, v3
// CHECK: error: invalid operand for instruction
// Immediate src1
v_mul_i32_i24_e64 v1, v2, 100
// CHECK: error: invalid operand for instruction
AMDGPU: Add sdst operand to VOP2b instructions The VOP3 encoding of these allows any SGPR pair for the i1 output, but this was forced before to always use vcc. This doesn't yet try to use this, but does add the operand to the definitions so the main change is adding vcc to the output of the VOP2 encoding. llvm-svn: 246358
2015-08-29 15:16:50 +08:00
v_add_i32_e32 v1, s[0:1], v2, v3
// CHECK: error: invalid operand for instruction
AMDGPU/SI: Fix input vcc operand for VOP2b instructions Adds vcc to output string input for e32. Allows option of using e64 encoding with assembler. Also fixes these instructions not implicitly reading exec. llvm-svn: 247074
2015-09-09 05:15:00 +08:00
v_addc_u32_e32 v1, vcc, v2, v3, s[2:3]
// CHECK: error: invalid operand for instruction
v_addc_u32_e32 v1, s[0:1], v2, v3, s[2:3]
// CHECK: error: invalid operand for instruction
v_addc_u32_e32 v1, vcc, v2, v3, -1
// CHECK: error: invalid operand for instruction
v_addc_u32_e32 v1, vcc, v2, v3, 123
// CHECK: error: invalid operand for instruction
v_addc_u32_e32 v1, vcc, v2, v3, s0
// CHECK: error: invalid operand for instruction
v_addc_u32_e32 v1, -1, v2, v3, s0
// CHECK: error: invalid operand for instruction
v_addc_u32_e64 v1, s[0:1], v2, v3, 123
// CHECK: error: invalid operand for instruction
v_addc_u32 v1, s[0:1], v2, v3, 123
// CHECK: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
// TODO: Constant bus restrictions