maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/ARM/expand-pseudos.mir

76 lines
1.8 KiB
Plaintext
Raw Normal View History

[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
2017-09-06 06:54:06 +08:00
# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
--- |
target triple = "armv7---gnueabi"
define i32 @test1(i32 %x) {
entry:
unreachable
}
define i32 @test2(i32 %x) {
entry:
unreachable
}
define i32 @test3(i32 %x) {
entry:
unreachable
}
...
---
name: test1
alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '%r0', virtual-reg: '' }
body: |
bb.0.entry:
liveins: %r0
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-12-01 00:12:24 +08:00
%r1 = MOVi 2, 14, %noreg, %noreg
CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
2017-09-06 06:54:06 +08:00
%r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-12-01 00:12:24 +08:00
%r0 = MOVr killed %r1, 14, %noreg, %noreg
BX_RET 14, %noreg, implicit %r0
[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
2017-09-06 06:54:06 +08:00
...
---
name: test2
alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '%r0', virtual-reg: '' }
body: |
bb.0.entry:
liveins: %r0
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-12-01 00:12:24 +08:00
%r1 = MOVi 2, 14, %noreg, %noreg
CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
2017-09-06 06:54:06 +08:00
%r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-12-01 00:12:24 +08:00
%r0 = MOVr killed %r1, 14, %noreg, %noreg
BX_RET 14, %noreg, implicit %r0
[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
2017-09-06 06:54:06 +08:00
...
---
name: test3
alignment: 2
tracksRegLiveness: true
liveins:
- { reg: '%r0', virtual-reg: '' }
- { reg: '%r1', virtual-reg: '' }
body: |
bb.0.entry:
liveins: %r0, %r1
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-12-01 00:12:24 +08:00
CMPri %r1, 500, 14, %noreg, implicit-def %cpsr
[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
2017-09-06 06:54:06 +08:00
%r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-12-01 00:12:24 +08:00
BX_RET 14, %noreg, implicit %r0
[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
2017-09-06 06:54:06 +08:00
...
# CHECK-LABEL: name: test1
# CHECK: %r1 = MOVi16 500, 0, killed %cpsr, implicit killed %r1
# CHECK-LABEL: name: test2
# CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1
# CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr
# CHECK-LABEL: name: test3
[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
2017-12-01 00:12:24 +08:00
# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, %noreg, implicit killed %r0