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llvm-project/llvm/test/CodeGen/ARM/armv4.ll

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Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-07 03:39:36 +08:00
; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
Fix ARMv4 support ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
2017-08-29 04:20:47 +08:00
define i32 @test_return(i32 %a) nounwind readnone {
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-07 03:39:36 +08:00
entry:
Fix ARMv4 support ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
2017-08-29 04:20:47 +08:00
; ARM-LABEL: test_return
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-07 03:39:36 +08:00
; ARM: mov pc
Fix ARMv4 support ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
2017-08-29 04:20:47 +08:00
; THUMB-LABEL: test_return
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-07 03:39:36 +08:00
; THUMB: bx
ret i32 %a
}
Fix ARMv4 support ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
2017-08-29 04:20:47 +08:00
@helper = global i32 ()* null, align 4
define i32 @test_indirect() #0 {
entry:
; ARM-LABEL: test_indirect
; ARM: mov pc
; THUMB-LABEL: test_indirect
; THUMB: bx
%0 = load i32 ()*, i32 ()** @helper, align 4
%call = tail call i32 %0()
ret i32 %call
}