llvm-project/llvm/test/CodeGen/X86/cmpxchg16b.ll

; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s

; Basic 128-bit cmpxchg
define void @t1(i128* nocapture %p) nounwind ssp {
entry:
; CHECK: movl	$1, %ebx
; CHECK: lock
; CHECK-NEXT: cmpxchg16b
  %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
  ret void
}

; FIXME: Handle 128-bit atomicrmw/load atomic/store atomic
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660 2011-08-27 05:21:21 +08:00			`; RUN: llc < %s -march=x86-64 -mcpu=core2 \| FileCheck %s`

			`; Basic 128-bit cmpxchg`
			`define void @t1(i128* nocapture %p) nounwind ssp {`
			`entry:`
FileCheck hygiene. llvm-svn: 147580 2012-01-05 08:43:34 +08:00			`; CHECK: movl $1, %ebx`
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660 2011-08-27 05:21:21 +08:00			`; CHECK: lock`
			`; CHECK-NEXT: cmpxchg16b`
IR: add a second ordering operand to cmpxhg for failure The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559 2014-03-11 18:48:52 +08:00			`%r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst`
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. llvm-svn: 138660 2011-08-27 05:21:21 +08:00			`ret void`
			`}`

			`; FIXME: Handle 128-bit atomicrmw/load atomic/store atomic`