2017-05-12 03:56:14 +08:00
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; RUN: llc -O0 < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
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target triple = "msp430---elf"
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@g_double = global double 123.0, align 8
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@g_float = global float 123.0, align 8
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@g_i32 = global i32 123, align 8
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@g_i64 = global i64 456, align 8
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@g_i16 = global i16 789, align 8
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define float @d2f() #0 {
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entry:
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; CHECK: d2f:
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; CHECK: call #__mspabi_cvtdf
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%0 = load volatile double, double* @g_double, align 8
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%1 = fptrunc double %0 to float
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ret float %1
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}
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define double @f2d() #0 {
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entry:
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; CHECK: f2d:
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; CHECK: call #__mspabi_cvtfd
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%0 = load volatile float, float* @g_float, align 8
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%1 = fpext float %0 to double
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ret double %1
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}
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define i32 @d2l() #0 {
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entry:
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; CHECK: d2l:
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; CHECK: call #__mspabi_fixdli
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%0 = load volatile double, double* @g_double, align 8
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%1 = fptosi double %0 to i32
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ret i32 %1
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}
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define i64 @d2ll() #0 {
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entry:
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; CHECK: d2ll:
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; CHECK: call #__mspabi_fixdlli
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%0 = load volatile double, double* @g_double, align 8
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%1 = fptosi double %0 to i64
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ret i64 %1
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}
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define i32 @d2ul() #0 {
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entry:
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; CHECK: d2ul:
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; CHECK: call #__mspabi_fixdul
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%0 = load volatile double, double* @g_double, align 8
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%1 = fptoui double %0 to i32
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ret i32 %1
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}
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define i64 @d2ull() #0 {
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entry:
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; CHECK: d2ull:
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; CHECK: call #__mspabi_fixdull
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%0 = load volatile double, double* @g_double, align 8
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%1 = fptoui double %0 to i64
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ret i64 %1
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}
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define i32 @f2l() #0 {
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entry:
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; CHECK: f2l:
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; CHECK: call #__mspabi_fixfli
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%0 = load volatile float, float* @g_float, align 8
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%1 = fptosi float %0 to i32
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ret i32 %1
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}
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define i64 @f2ll() #0 {
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entry:
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; CHECK: f2ll:
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; CHECK: call #__mspabi_fixflli
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%0 = load volatile float, float* @g_float, align 8
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%1 = fptosi float %0 to i64
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ret i64 %1
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}
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define i32 @f2ul() #0 {
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entry:
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; CHECK: f2ul:
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; CHECK: call #__mspabi_fixful
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%0 = load volatile float, float* @g_float, align 8
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%1 = fptoui float %0 to i32
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ret i32 %1
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}
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define i64 @f2ull() #0 {
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entry:
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; CHECK: f2ull:
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; CHECK: call #__mspabi_fixfull
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%0 = load volatile float, float* @g_float, align 8
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%1 = fptoui float %0 to i64
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ret i64 %1
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}
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define double @l2d() #0 {
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entry:
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; CHECK: l2d:
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; CHECK: call #__mspabi_fltlid
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%0 = load volatile i32, i32* @g_i32, align 8
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%1 = sitofp i32 %0 to double
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ret double %1
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}
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define double @ll2d() #0 {
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entry:
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; CHECK: ll2d:
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; CHECK: call #__mspabi_fltllid
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%0 = load volatile i64, i64* @g_i64, align 8
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%1 = sitofp i64 %0 to double
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ret double %1
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}
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define double @ul2d() #0 {
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entry:
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; CHECK: ul2d:
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; CHECK: call #__mspabi_fltuld
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%0 = load volatile i32, i32* @g_i32, align 8
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%1 = uitofp i32 %0 to double
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ret double %1
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}
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define double @ull2d() #0 {
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entry:
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; CHECK: ull2d:
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; CHECK: call #__mspabi_fltulld
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%0 = load volatile i64, i64* @g_i64, align 8
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%1 = uitofp i64 %0 to double
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ret double %1
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}
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define float @l2f() #0 {
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entry:
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; CHECK: l2f:
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; CHECK: call #__mspabi_fltlif
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%0 = load volatile i32, i32* @g_i32, align 8
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%1 = sitofp i32 %0 to float
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ret float %1
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}
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define float @ll2f() #0 {
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entry:
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; CHECK: ll2f:
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; CHECK: call #__mspabi_fltllif
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%0 = load volatile i64, i64* @g_i64, align 8
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%1 = sitofp i64 %0 to float
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ret float %1
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}
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define float @ul2f() #0 {
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entry:
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; CHECK: ul2f:
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; CHECK: call #__mspabi_fltulf
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%0 = load volatile i32, i32* @g_i32, align 8
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%1 = uitofp i32 %0 to float
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ret float %1
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}
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define float @ull2f() #0 {
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entry:
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; CHECK: ull2f:
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; CHECK: call #__mspabi_fltullf
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%0 = load volatile i64, i64* @g_i64, align 8
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%1 = uitofp i64 %0 to float
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ret float %1
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}
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define i1 @cmpd_oeq() #0 {
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entry:
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; CHECK: cmpd_oeq:
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; CHECK: call #__mspabi_cmpd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fcmp oeq double %0, 123.0
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ret i1 %1
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}
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define i1 @cmpd_une() #0 {
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entry:
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; CHECK: cmpd_une:
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; CHECK: call #__mspabi_cmpd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fcmp une double %0, 123.0
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ret i1 %1
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}
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define i1 @cmpd_oge() #0 {
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entry:
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; CHECK: cmpd_oge:
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; CHECK: call #__mspabi_cmpd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fcmp oge double %0, 123.0
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ret i1 %1
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}
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define i1 @cmpd_olt() #0 {
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entry:
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; CHECK: cmpd_olt:
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; CHECK: call #__mspabi_cmpd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fcmp olt double %0, 123.0
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ret i1 %1
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}
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define i1 @cmpd_ole() #0 {
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entry:
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; CHECK: cmpd_ole:
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; CHECK: call #__mspabi_cmpd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fcmp ole double %0, 123.0
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ret i1 %1
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}
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define i1 @cmpd_ogt() #0 {
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entry:
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; CHECK: cmpd_ogt:
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; CHECK: call #__mspabi_cmpd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fcmp ogt double %0, 123.0
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ret i1 %1
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}
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define i1 @cmpf_oeq() #0 {
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entry:
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; CHECK: cmpf_oeq:
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; CHECK: call #__mspabi_cmpf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fcmp oeq float %0, 123.0
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ret i1 %1
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}
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define i1 @cmpf_une() #0 {
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entry:
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; CHECK: cmpf_une:
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; CHECK: call #__mspabi_cmpf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fcmp une float %0, 123.0
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ret i1 %1
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}
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define i1 @cmpf_oge() #0 {
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entry:
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; CHECK: cmpf_oge:
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; CHECK: call #__mspabi_cmpf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fcmp oge float %0, 123.0
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ret i1 %1
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}
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define i1 @cmpf_olt() #0 {
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entry:
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; CHECK: cmpf_olt:
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; CHECK: call #__mspabi_cmpf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fcmp olt float %0, 123.0
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ret i1 %1
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}
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define i1 @cmpf_ole() #0 {
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entry:
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; CHECK: cmpf_ole:
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; CHECK: call #__mspabi_cmpf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fcmp ole float %0, 123.0
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ret i1 %1
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}
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define i1 @cmpf_ogt() #0 {
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entry:
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; CHECK: cmpf_ogt:
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; CHECK: call #__mspabi_cmpf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fcmp ogt float %0, 123.0
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ret i1 %1
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}
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define double @addd() #0 {
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entry:
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; CHECK: addd:
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; CHECK: call #__mspabi_addd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fadd double %0, 123.0
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ret double %1
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}
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define float @addf() #0 {
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entry:
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; CHECK: addf:
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; CHECK: call #__mspabi_addf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fadd float %0, 123.0
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ret float %1
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}
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define double @divd() #0 {
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entry:
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; CHECK: divd:
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; CHECK: call #__mspabi_divd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fdiv double %0, 123.0
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ret double %1
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}
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define float @divf() #0 {
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entry:
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; CHECK: divf:
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; CHECK: call #__mspabi_divf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fdiv float %0, 123.0
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ret float %1
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}
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define double @mpyd() #0 {
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entry:
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; CHECK: mpyd:
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; CHECK: call #__mspabi_mpyd
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%0 = load volatile double, double* @g_double, align 8
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%1 = fmul double %0, 123.0
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ret double %1
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}
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define float @mpyf() #0 {
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entry:
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; CHECK: mpyf:
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; CHECK: call #__mspabi_mpyf
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%0 = load volatile float, float* @g_float, align 8
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%1 = fmul float %0, 123.0
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ret float %1
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}
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define double @subd() #0 {
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entry:
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; CHECK: subd:
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; CHECK: call #__mspabi_subd
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%0 = load volatile double, double* @g_double, align 8
|
|
|
|
%1 = fsub double %0, %0
|
|
|
|
|
|
|
|
ret double %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define float @subf() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: subf:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_subf
|
|
|
|
%0 = load volatile float, float* @g_float, align 8
|
|
|
|
%1 = fsub float %0, %0
|
|
|
|
|
|
|
|
ret float %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i16 @divi() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: divi:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_divi
|
|
|
|
%0 = load volatile i16, i16* @g_i16, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i16, i16* @g_i16, align 8
|
|
|
|
%2 = sdiv i16 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i16 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @divli() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: divli:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_divli
|
|
|
|
%0 = load volatile i32, i32* @g_i32, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i32, i32* @g_i32, align 8
|
|
|
|
%2 = sdiv i32 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i32 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @divlli() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: divlli:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_divlli
|
|
|
|
%0 = load volatile i64, i64* @g_i64, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i64, i64* @g_i64, align 8
|
|
|
|
%2 = sdiv i64 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i64 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i16 @divu() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: divu:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_divu
|
|
|
|
%0 = load volatile i16, i16* @g_i16, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i16, i16* @g_i16, align 8
|
|
|
|
%2 = udiv i16 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i16 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @divul() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: divul:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_divul
|
|
|
|
%0 = load volatile i32, i32* @g_i32, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i32, i32* @g_i32, align 8
|
|
|
|
%2 = udiv i32 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i32 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @divull() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: divull:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_divull
|
|
|
|
%0 = load volatile i64, i64* @g_i64, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i64, i64* @g_i64, align 8
|
|
|
|
%2 = udiv i64 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i64 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i16 @remi() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: remi:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_remi
|
|
|
|
%0 = load volatile i16, i16* @g_i16, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i16, i16* @g_i16, align 8
|
|
|
|
%2 = srem i16 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i16 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @remli() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: remli:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_remli
|
|
|
|
%0 = load volatile i32, i32* @g_i32, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i32, i32* @g_i32, align 8
|
|
|
|
%2 = srem i32 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i32 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @remlli() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: remlli:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_remlli
|
|
|
|
%0 = load volatile i64, i64* @g_i64, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i64, i64* @g_i64, align 8
|
|
|
|
%2 = srem i64 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i64 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i16 @remu() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: remu:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_remu
|
|
|
|
%0 = load volatile i16, i16* @g_i16, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i16, i16* @g_i16, align 8
|
|
|
|
%2 = urem i16 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i16 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @remul() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: remul:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_remul
|
|
|
|
%0 = load volatile i32, i32* @g_i32, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i32, i32* @g_i32, align 8
|
|
|
|
%2 = urem i32 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i32 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @remull() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: remull:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_remull
|
|
|
|
%0 = load volatile i64, i64* @g_i64, align 8
|
2018-08-29 19:18:14 +08:00
|
|
|
%1 = load volatile i64, i64* @g_i64, align 8
|
|
|
|
%2 = urem i64 %0, %1
|
2017-05-12 03:56:14 +08:00
|
|
|
|
2018-08-29 19:18:14 +08:00
|
|
|
ret i64 %2
|
2017-05-12 03:56:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define i16 @mpyi() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: mpyi:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_mpyi
|
|
|
|
%0 = load volatile i16, i16* @g_i16, align 8
|
|
|
|
%1 = mul i16 %0, %0
|
|
|
|
|
|
|
|
ret i16 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @mpyli() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: mpyli:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_mpyl
|
|
|
|
%0 = load volatile i32, i32* @g_i32, align 8
|
|
|
|
%1 = mul i32 %0, %0
|
|
|
|
|
|
|
|
ret i32 %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @mpylli() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK: mpylli:
|
|
|
|
|
|
|
|
; CHECK: call #__mspabi_mpyll
|
|
|
|
%0 = load volatile i64, i64* @g_i64, align 8
|
|
|
|
%1 = mul i64 %0, %0
|
|
|
|
|
|
|
|
ret i64 %1
|
|
|
|
}
|
|
|
|
|
2018-11-17 03:36:15 +08:00
|
|
|
@i = external global i32, align 2
|
|
|
|
|
|
|
|
define i32 @srll() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK-LABEL: srll:
|
|
|
|
; CHECK: call #__mspabi_srll
|
|
|
|
%0 = load volatile i32, i32* @g_i32, align 2
|
|
|
|
%1 = load volatile i32, i32* @i, align 2
|
|
|
|
%shr = lshr i32 %0, %1
|
|
|
|
|
|
|
|
ret i32 %shr
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @sral() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK-LABEL: sral:
|
|
|
|
; CHECK: call #__mspabi_sral
|
|
|
|
%0 = load volatile i32, i32* @g_i32, align 2
|
|
|
|
%1 = load volatile i32, i32* @i, align 2
|
|
|
|
%shr = ashr i32 %0, %1
|
|
|
|
|
|
|
|
ret i32 %shr
|
|
|
|
}
|
|
|
|
|
|
|
|
define i32 @slll() #0 {
|
|
|
|
entry:
|
|
|
|
; CHECK-LABEL: slll:
|
|
|
|
; CHECK: call #__mspabi_slll
|
|
|
|
%0 = load volatile i32, i32* @g_i32, align 2
|
|
|
|
%1 = load volatile i32, i32* @i, align 2
|
|
|
|
%shr = shl i32 %0, %1
|
|
|
|
|
|
|
|
ret i32 %shr
|
|
|
|
}
|
|
|
|
|
2017-05-12 03:56:14 +08:00
|
|
|
attributes #0 = { nounwind }
|