maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/ARM/signext-inreg.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

18 lines
611 B
LLVM
Raw Normal View History

[NFC] Add one test to verify the sign_extend of vector type.
2019-11-11 17:44:13 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal' For now, we didn't set the default operation action for SIGN_EXTEND_INREG for vector type, which is 0 by default, that is legal. However, most target didn't have native instructions to support this opcode. It should be set as expand by default, as what we did for ANY_EXTEND_VECTOR_INREG. Differential Revision: https://reviews.llvm.org/D70000
2020-01-03 11:26:41 +08:00
; RUN: llc < %s -mtriple=armv8 | FileCheck %s
[NFC] Add one test to verify the sign_extend of vector type.
2019-11-11 17:44:13 +08:00
define <4 x i32> @test(<4 x i32> %m) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0: @ %entry
[DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal' For now, we didn't set the default operation action for SIGN_EXTEND_INREG for vector type, which is 0 by default, that is legal. However, most target didn't have native instructions to support this opcode. It should be set as expand by default, as what we did for ANY_EXTEND_VECTOR_INREG. Differential Revision: https://reviews.llvm.org/D70000
2020-01-03 11:26:41 +08:00
; CHECK-NEXT: vmov d17, r2, r3
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: vshl.i32 q8, q8, #24
; CHECK-NEXT: vshr.s32 q8, q8, #24
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
[NFC] Add one test to verify the sign_extend of vector type.
2019-11-11 17:44:13 +08:00
; CHECK-NEXT: bx lr
entry:
%shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
%shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
ret <4 x i32> %shr
}