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llvm-project/llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll

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When the "true" and "false" blocks of a diamond if-conversion are the same, do not double-count the duplicate instructions by counting once from the beginning and again from the end. Keep track of where the duplicates from the beginning ended and don't go past that point when counting duplicates at the end. Radar 8589805. This change causes one of the MC/ARM/simple-fp-encoding tests to produce different (better!) code without the vmovne instruction being tested. I changed the test to produce vmovne and vmoveq instructions but moving between register files in the opposite direction. That's not quite the same but predicated versions of those instructions weren't being tested before, so at least the test coverage is not any worse, just different. llvm-svn: 117333
2010-10-26 08:02:24 +08:00
; RUN: llc < %s -mtriple=armv6-apple-darwin -mcpu=arm1136jf-s | FileCheck %s
; Radar 8589805: Counting the number of microcoded operations, such as for an
; LDM instruction, was causing an assertion failure because the microop count
; was being treated as an instruction count.
Rewrite stack callee saved spills and restores to use push/pop instructions. Remove movePastCSLoadStoreOps and associated code for simple pointer increments. Update routines that depended upon other opcodes for save/restore. Adjust all testcases accordingly. llvm-svn: 119725
2010-11-19 03:40:05 +08:00
; CHECK: push
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- effect that we get proper instruction printing using the "pop" mnemonic for it. llvm-svn: 127502
2011-03-12 06:51:41 +08:00
; CHECK: pop
; CHECK: pop
; CHECK: pop
When the "true" and "false" blocks of a diamond if-conversion are the same, do not double-count the duplicate instructions by counting once from the beginning and again from the end. Keep track of where the duplicates from the beginning ended and don't go past that point when counting duplicates at the end. Radar 8589805. This change causes one of the MC/ARM/simple-fp-encoding tests to produce different (better!) code without the vmovne instruction being tested. I changed the test to produce vmovne and vmoveq instructions but moving between register files in the opposite direction. That's not quite the same but predicated versions of those instructions weren't being tested before, so at least the test coverage is not any worse, just different. llvm-svn: 117333
2010-10-26 08:02:24 +08:00
define i32 @test(i32 %x) {
entry:
%0 = tail call signext i16 undef(i32* undef)
AArch64 & ARM: remove undefined behaviour from some tests. llvm-svn: 209880
2014-05-30 16:59:55 +08:00
switch i32 %x, label %bb3 [
When the "true" and "false" blocks of a diamond if-conversion are the same, do not double-count the duplicate instructions by counting once from the beginning and again from the end. Keep track of where the duplicates from the beginning ended and don't go past that point when counting duplicates at the end. Radar 8589805. This change causes one of the MC/ARM/simple-fp-encoding tests to produce different (better!) code without the vmovne instruction being tested. I changed the test to produce vmovne and vmoveq instructions but moving between register files in the opposite direction. That's not quite the same but predicated versions of those instructions weren't being tested before, so at least the test coverage is not any worse, just different. llvm-svn: 117333
2010-10-26 08:02:24 +08:00
i32 0, label %bb4
i32 1, label %bb1
i32 2, label %bb2
]
bb1:
ret i32 1
bb2:
ret i32 2
bb3:
ret i32 1
bb4:
ret i32 3
}