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llvm-project/llvm/test/CodeGen/X86/pr28489.ll

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[X86] Disable FixupSetCC for CodeGenOpt::None It is an optimization pass, and should not run at -O0. Especially since Fast RA will not do the required register coalescing anyway, so it's a loss even from the optimization standpoint. This also works around (but doesn't quite fix) PR28489. llvm-svn: 275099
2016-07-12 04:40:44 +08:00
; ; RUN: llc < %s -mtriple=i686-pc-linux -O0 | FileCheck %s
declare void @g(i32, i1)
;CHECK-LABEL: f:
;CHECK: cmpxchg8b
Relax fast register allocator related test cases; NFC - Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
2018-10-30 04:10:42 +08:00
;CHECK: sete [[REG:%[abcd]l]]
;CHECK: movzbl [[REG]]
[X86] Disable FixupSetCC for CodeGenOpt::None It is an optimization pass, and should not run at -O0. Especially since Fast RA will not do the required register coalescing anyway, so it's a loss even from the optimization standpoint. This also works around (but doesn't quite fix) PR28489. llvm-svn: 275099
2016-07-12 04:40:44 +08:00
define void @f(i64* %arg, i64 %arg1) {
entry:
%tmp5 = cmpxchg i64* %arg, i64 %arg1, i64 %arg1 seq_cst seq_cst
%tmp7 = extractvalue { i64, i1 } %tmp5, 1
%tmp9 = zext i1 %tmp7 to i32
call void @g(i32 %tmp9, i1 %tmp7)
ret void
}