maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/combine-adc.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

71 lines
2.1 KiB
LLVM
Raw Normal View History

[X86] Add PR40483 test cases Demonstrate failure to merge ISD::ADD(x,y)/X86ISD::ADD(x,y) + ISD::SUB(x,y)/X86ISD::SUB(x,y) equivalent ops llvm-svn: 354758
2019-02-25 05:13:29 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64
define i32 @PR40483_add1(i32*, i32) nounwind {
; X86-LABEL: PR40483_add1:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483) Avoid ADD/SUB instruction duplication by reusing the X86ISD::ADD/SUB results. Includes ADD commutation - I tried to include NEG+SUB SUB commutation as well but this causes regressions as we don't have good combine coverage to simplify X86ISD::SUB. Differential Revision: https://reviews.llvm.org/D58597 llvm-svn: 354771
2019-02-25 19:19:37 +08:00
; X86-NEXT: movl (%ecx), %eax
; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: jae .LBB0_2
; X86-NEXT: # %bb.1:
[X86] Add PR40483 test cases Demonstrate failure to merge ISD::ADD(x,y)/X86ISD::ADD(x,y) + ISD::SUB(x,y)/X86ISD::SUB(x,y) equivalent ops llvm-svn: 354758
2019-02-25 05:13:29 +08:00
; X86-NEXT: xorl %eax, %eax
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483) Avoid ADD/SUB instruction duplication by reusing the X86ISD::ADD/SUB results. Includes ADD commutation - I tried to include NEG+SUB SUB commutation as well but this causes regressions as we don't have good combine coverage to simplify X86ISD::SUB. Differential Revision: https://reviews.llvm.org/D58597 llvm-svn: 354771
2019-02-25 19:19:37 +08:00
; X86-NEXT: .LBB0_2:
[X86] Add PR40483 test cases Demonstrate failure to merge ISD::ADD(x,y)/X86ISD::ADD(x,y) + ISD::SUB(x,y)/X86ISD::SUB(x,y) equivalent ops llvm-svn: 354758
2019-02-25 05:13:29 +08:00
; X86-NEXT: retl
;
; X64-LABEL: PR40483_add1:
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483) Avoid ADD/SUB instruction duplication by reusing the X86ISD::ADD/SUB results. Includes ADD commutation - I tried to include NEG+SUB SUB commutation as well but this causes regressions as we don't have good combine coverage to simplify X86ISD::SUB. Differential Revision: https://reviews.llvm.org/D58597 llvm-svn: 354771
2019-02-25 19:19:37 +08:00
; X64-NEXT: addl (%rdi), %esi
; X64-NEXT: movl %esi, (%rdi)
; X64-NEXT: cmovael %esi, %eax
[X86] Add PR40483 test cases Demonstrate failure to merge ISD::ADD(x,y)/X86ISD::ADD(x,y) + ISD::SUB(x,y)/X86ISD::SUB(x,y) equivalent ops llvm-svn: 354758
2019-02-25 05:13:29 +08:00
; X64-NEXT: retq
%3 = load i32, i32* %0, align 8
%4 = tail call { i8, i32 } @llvm.x86.addcarry.32(i8 0, i32 %3, i32 %1)
%5 = extractvalue { i8, i32 } %4, 1
store i32 %5, i32* %0, align 8
%6 = extractvalue { i8, i32 } %4, 0
%7 = icmp eq i8 %6, 0
%8 = add i32 %1, %3
%9 = or i32 %5, %8
%10 = select i1 %7, i32 %9, i32 0
ret i32 %10
}
define i32 @PR40483_add2(i32*, i32) nounwind {
; X86-LABEL: PR40483_add2:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483) Avoid ADD/SUB instruction duplication by reusing the X86ISD::ADD/SUB results. Includes ADD commutation - I tried to include NEG+SUB SUB commutation as well but this causes regressions as we don't have good combine coverage to simplify X86ISD::SUB. Differential Revision: https://reviews.llvm.org/D58597 llvm-svn: 354771
2019-02-25 19:19:37 +08:00
; X86-NEXT: movl (%edx), %ecx
[X86] Add PR40483 test cases Demonstrate failure to merge ISD::ADD(x,y)/X86ISD::ADD(x,y) + ISD::SUB(x,y)/X86ISD::SUB(x,y) equivalent ops llvm-svn: 354758
2019-02-25 05:13:29 +08:00
; X86-NEXT: xorl %eax, %eax
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483) Avoid ADD/SUB instruction duplication by reusing the X86ISD::ADD/SUB results. Includes ADD commutation - I tried to include NEG+SUB SUB commutation as well but this causes regressions as we don't have good combine coverage to simplify X86ISD::SUB. Differential Revision: https://reviews.llvm.org/D58597 llvm-svn: 354771
2019-02-25 19:19:37 +08:00
; X86-NEXT: addl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, (%edx)
[X86] Add PR40483 test cases Demonstrate failure to merge ISD::ADD(x,y)/X86ISD::ADD(x,y) + ISD::SUB(x,y)/X86ISD::SUB(x,y) equivalent ops llvm-svn: 354758
2019-02-25 05:13:29 +08:00
; X86-NEXT: jae .LBB1_2
; X86-NEXT: # %bb.1:
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: .LBB1_2:
; X86-NEXT: retl
;
; X64-LABEL: PR40483_add2:
; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483) Avoid ADD/SUB instruction duplication by reusing the X86ISD::ADD/SUB results. Includes ADD commutation - I tried to include NEG+SUB SUB commutation as well but this causes regressions as we don't have good combine coverage to simplify X86ISD::SUB. Differential Revision: https://reviews.llvm.org/D58597 llvm-svn: 354771
2019-02-25 19:19:37 +08:00
; X64-NEXT: addl (%rdi), %esi
; X64-NEXT: movl %esi, (%rdi)
; X64-NEXT: cmovbl %esi, %eax
[X86] Add PR40483 test cases Demonstrate failure to merge ISD::ADD(x,y)/X86ISD::ADD(x,y) + ISD::SUB(x,y)/X86ISD::SUB(x,y) equivalent ops llvm-svn: 354758
2019-02-25 05:13:29 +08:00
; X64-NEXT: retq
%3 = load i32, i32* %0, align 8
%4 = tail call { i8, i32 } @llvm.x86.addcarry.32(i8 0, i32 %3, i32 %1)
%5 = extractvalue { i8, i32 } %4, 1
store i32 %5, i32* %0, align 8
%6 = extractvalue { i8, i32 } %4, 0
%7 = icmp eq i8 %6, 0
%8 = add i32 %3, %1
%9 = or i32 %5, %8
%10 = select i1 %7, i32 0, i32 %9
ret i32 %10
}
declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32)