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llvm-project/llvm/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll

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[X86] Regenerate GPR:XMM bitcast test llvm-svn: 325684
2018-02-21 23:05:47 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Fix register-dependent X86 tests. llvm-svn: 128867
2011-04-05 08:32:44 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | FileCheck %s
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 07:57:10 +08:00
@R = external global x86_mmx ; <x86_mmx*> [#uses=1]
Allow a GR64 to be moved into an MMX register via the "movd" instruction. Still need to have JIT generate this code. llvm-svn: 37863
2007-07-04 08:19:54 +08:00
no need for eh info llvm-svn: 50658
2008-05-06 02:24:33 +08:00
define void @foo(<1 x i64> %A, <1 x i64> %B) nounwind {
[X86] Regenerate GPR:XMM bitcast test llvm-svn: 325684
2018-02-21 23:05:47 +08:00
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movq %rsi, %mm0
; CHECK-NEXT: movq %rdi, %mm1
; CHECK-NEXT: paddusw %mm0, %mm1
; CHECK-NEXT: movq _R@{{.*}}(%rip), %rax
; CHECK-NEXT: movq %mm1, (%rax)
; CHECK-NEXT: emms
; CHECK-NEXT: retq
Allow a GR64 to be moved into an MMX register via the "movd" instruction. Still need to have JIT generate this code. llvm-svn: 37863
2007-07-04 08:19:54 +08:00
entry:
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 07:57:10 +08:00
%tmp4 = bitcast <1 x i64> %B to x86_mmx ; <<4 x i16>> [#uses=1]
%tmp6 = bitcast <1 x i64> %A to x86_mmx ; <<4 x i16>> [#uses=1]
%tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w( x86_mmx %tmp6, x86_mmx %tmp4 ) ; <x86_mmx> [#uses=1]
store x86_mmx %tmp7, x86_mmx* @R
Allow a GR64 to be moved into an MMX register via the "movd" instruction. Still need to have JIT generate this code. llvm-svn: 37863
2007-07-04 08:19:54 +08:00
tail call void @llvm.x86.mmx.emms( )
ret void
}
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 07:57:10 +08:00
declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
Allow a GR64 to be moved into an MMX register via the "movd" instruction. Still need to have JIT generate this code. llvm-svn: 37863
2007-07-04 08:19:54 +08:00
declare void @llvm.x86.mmx.emms()