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llvm-project/llvm/test/CodeGen/ARM/div.ll

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[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | FileCheck %s -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | FileCheck %s -check-prefix=CHECK-SWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f1(i32 %a, i32 %b) {
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
entry:
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; CHECK-SWDIV: f1
; CHECK-SWDIV: __divsi3
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
Cortex-R5 can issue Thumb2 integer division instructions. llvm-svn: 183275
2013-06-05 06:52:09 +08:00
; CHECK-HWDIV: f1
; CHECK-HWDIV: sdiv
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f2(i32 %a, i32 %b) {
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
entry:
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; CHECK-SWDIV: f2
; CHECK-SWDIV: __udivsi3
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
Cortex-R5 can issue Thumb2 integer division instructions. llvm-svn: 183275
2013-06-05 06:52:09 +08:00
; CHECK-HWDIV: f2
; CHECK-HWDIV: udiv
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f3(i32 %a, i32 %b) {
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
entry:
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; CHECK-SWDIV: f3
; CHECK-SWDIV: __modsi3
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
Cortex-R5 can issue Thumb2 integer division instructions. llvm-svn: 183275
2013-06-05 06:52:09 +08:00
; CHECK-HWDIV: f3
; CHECK-HWDIV: sdiv
; CHECK-HWDIV: mls
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
define i32 @f4(i32 %a, i32 %b) {
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
entry:
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
; CHECK-SWDIV: f4
; CHECK-SWDIV: __umodsi3
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
Cortex-R5 can issue Thumb2 integer division instructions. llvm-svn: 183275
2013-06-05 06:52:09 +08:00
; CHECK-HWDIV: f4
; CHECK-HWDIV: udiv
; CHECK-HWDIV: mls
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00
%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM llvm-svn: 31014
2006-10-18 05:05:33 +08:00
}
Remove llvm-upgrade. llvm-svn: 47238
2008-02-18 04:02:20 +08:00