[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
llvm-svn: 330014
2018-04-13 20:56:14 +08:00
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-8, 7].
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st1d z25.d, p4, [x16, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1d z25.d, p4, [x16, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Immediate out of upper bound [-8, 7].
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st1d z16.d, p4, [x2, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1d z16.d, p4, [x2, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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2019-06-07 16:46:56 +08:00
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// Invalid predicate
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[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
llvm-svn: 330014
2018-04-13 20:56:14 +08:00
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st1d z12.d, p8, [x4, #14, MUL VL]
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2019-06-07 16:37:00 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
llvm-svn: 330014
2018-04-13 20:56:14 +08:00
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// CHECK-NEXT: st1d z12.d, p8, [x4, #14, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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2019-06-07 16:46:56 +08:00
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st1d z12.d, p7.b, [x4, #14, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st1d z12.d, p7.b, [x4, #14, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z12.d, p7.q, [x4, #14, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st1d z12.d, p7.q, [x4, #14, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
llvm-svn: 330014
2018-04-13 20:56:14 +08:00
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// --------------------------------------------------------------------------//
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// Invalid vector list
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st1d { }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: st1d { }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d { z1.d, z2.d }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1d { z1.d, z2.d }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d { v0.2d }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1d { v0.2d }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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2018-05-01 21:36:03 +08:00
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st1d z0.d, p0, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, x0, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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2018-05-02 21:00:30 +08:00
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// --------------------------------------------------------------------------//
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// Invalid scalar + vector addressing modes
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st1d z0.d, p0, [x0, z0.s]
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[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
llvm-svn: 332483
2018-05-16 23:45:17 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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2018-05-02 21:00:30 +08:00
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// CHECK-NEXT: st1d z0.d, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, z0.d, uxtw #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, uxtw #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, z0.d, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
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// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [x0, z0.d, lsl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
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// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector + immediate addressing modes
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st1d z0.s, p0, [z0.s]
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[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
llvm-svn: 332483
2018-05-16 23:45:17 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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2018-05-02 21:00:30 +08:00
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// CHECK-NEXT: st1d z0.s, p0, [z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.s, p0, [z0.s, #8]
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[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
llvm-svn: 332483
2018-05-16 23:45:17 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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2018-05-02 21:00:30 +08:00
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// CHECK-NEXT: st1d z0.s, p0, [z0.s, #8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #-8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #-8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #249]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #249]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #256]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #256]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1d z0.d, p0, [z0.d, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
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// CHECK-NEXT: st1d z0.d, p0, [z0.d, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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2018-07-31 00:05:45 +08:00
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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st1d { z31.d }, p7, [z31.d, #248]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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st1d { z31.d }, p7, [z31.d, #248]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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