2016-02-12 03:43:04 +08:00
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//===-- X86FixupBWInsts.cpp - Fixup Byte or Word instructions -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines the pass that looks through the machine instructions
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/// late in the compilation, and finds byte or word instructions that
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/// can be profitably replaced with 32 bit instructions that give equivalent
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/// results for the bits of the results that are used. There are two possible
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/// reasons to do this.
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///
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/// One reason is to avoid false-dependences on the upper portions
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/// of the registers. Only instructions that have a destination register
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/// which is not in any of the source registers can be affected by this.
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/// Any instruction where one of the source registers is also the destination
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/// register is unaffected, because it has a true dependence on the source
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/// register already. So, this consideration primarily affects load
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/// instructions and register-to-register moves. It would
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/// seem like cmov(s) would also be affected, but because of the way cmov is
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/// really implemented by most machines as reading both the destination and
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/// and source regsters, and then "merging" the two based on a condition,
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/// it really already should be considered as having a true dependence on the
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/// destination register as well.
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///
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/// The other reason to do this is for potential code size savings. Word
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/// operations need an extra override byte compared to their 32 bit
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/// versions. So this can convert many word operations to their larger
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/// size, saving a byte in encoding. This could introduce partial register
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/// dependences where none existed however. As an example take:
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/// orw ax, $0x1000
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/// addw ax, $3
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/// now if this were to get transformed into
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/// orw ax, $1000
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/// addl eax, $3
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/// because the addl encodes shorter than the addw, this would introduce
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/// a use of a register that was only partially written earlier. On older
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/// Intel processors this can be quite a performance penalty, so this should
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/// probably only be done when it can be proven that a new partial dependence
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/// wouldn't be created, or when your know a newer processor is being
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/// targeted, or when optimizing for minimum code size.
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///
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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2016-04-26 08:00:48 +08:00
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#include "llvm/CodeGen/LivePhysRegs.h"
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2016-02-12 03:43:04 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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2016-05-07 09:11:10 +08:00
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#define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup"
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#define FIXUPBW_NAME "x86-fixup-bw-insts"
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#define DEBUG_TYPE FIXUPBW_NAME
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2016-02-12 03:43:04 +08:00
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// Option to allow this optimization pass to have fine-grained control.
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static cl::opt<bool>
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FixupBWInsts("fixup-byte-word-insts",
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cl::desc("Change byte and word instructions to larger sizes"),
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2016-04-09 02:58:29 +08:00
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cl::init(true), cl::Hidden);
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2016-02-12 03:43:04 +08:00
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namespace {
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class FixupBWInstPass : public MachineFunctionPass {
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2016-05-07 01:28:47 +08:00
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/// Loop over all of the instructions in the basic block replacing applicable
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/// byte or word instructions with better alternatives.
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2016-04-26 08:00:48 +08:00
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void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
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2016-02-12 03:43:04 +08:00
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2016-05-07 01:28:47 +08:00
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/// This sets the \p SuperDestReg to the 32 bit super reg of the original
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/// destination register of the MachineInstr passed in. It returns true if
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/// that super register is dead just prior to \p OrigMI, and false if not.
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2016-05-07 01:28:42 +08:00
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bool getSuperRegDestIfDead(MachineInstr *OrigMI,
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2016-02-12 03:43:04 +08:00
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unsigned &SuperDestReg) const;
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2016-05-07 01:28:47 +08:00
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/// Change the MachineInstr \p MI into the equivalent extending load to 32 bit
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/// register if it is safe to do so. Return the replacement instruction if
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/// OK, otherwise return nullptr.
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2016-05-07 01:28:42 +08:00
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MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *MI) const;
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2016-02-12 03:43:04 +08:00
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2016-05-07 09:11:17 +08:00
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/// Change the MachineInstr \p MI into the equivalent 32-bit copy if it is
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/// safe to do so. Return the replacement instruction if OK, otherwise return
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/// nullptr.
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MachineInstr *tryReplaceCopy(MachineInstr *MI) const;
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2016-06-16 00:03:06 +08:00
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// Change the MachineInstr \p MI into an eqivalent 32 bit instruction if
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// possible. Return the replacement instruction if OK, return nullptr
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// otherwise. Set WasCandidate to true or false depending on whether the
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// MI was a candidate for this sort of transformation.
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MachineInstr *tryReplaceInstr(MachineInstr *MI, MachineBasicBlock &MBB,
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bool &WasCandidate) const;
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2016-02-12 03:43:04 +08:00
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public:
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2016-05-07 09:11:10 +08:00
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static char ID;
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2016-10-01 10:56:57 +08:00
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StringRef getPassName() const override { return FIXUPBW_DESC; }
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2016-05-07 09:11:10 +08:00
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FixupBWInstPass() : MachineFunctionPass(ID) {
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initializeFixupBWInstPassPass(*PassRegistry::getPassRegistry());
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}
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2016-02-12 03:43:04 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineLoopInfo>(); // Machine loop info is used to
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// guide some heuristics.
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2016-05-07 01:28:47 +08:00
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/// Loop over all of the basic blocks, replacing byte and word instructions by
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/// equivalent 32 bit instructions where performance or code size can be
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/// improved.
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2016-02-12 03:43:04 +08:00
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bool runOnMachineFunction(MachineFunction &MF) override;
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2016-04-05 01:09:25 +08:00
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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2016-08-25 09:27:13 +08:00
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MachineFunctionProperties::Property::NoVRegs);
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2016-04-05 01:09:25 +08:00
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}
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2016-02-12 03:43:04 +08:00
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private:
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MachineFunction *MF;
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/// Machine instruction info used throughout the class.
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const X86InstrInfo *TII;
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/// Local member for function's OptForSize attribute.
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bool OptForSize;
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/// Machine loop info used for guiding some heruistics.
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MachineLoopInfo *MLI;
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2016-04-26 08:00:48 +08:00
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/// Register Liveness information after the current instruction.
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LivePhysRegs LiveRegs;
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2016-02-12 03:43:04 +08:00
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};
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char FixupBWInstPass::ID = 0;
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}
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2016-05-07 09:11:10 +08:00
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INITIALIZE_PASS(FixupBWInstPass, FIXUPBW_NAME, FIXUPBW_DESC, false, false)
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2016-02-12 03:43:04 +08:00
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FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); }
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bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
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2016-04-27 05:44:24 +08:00
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if (!FixupBWInsts || skipFunction(*MF.getFunction()))
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2016-02-12 03:43:04 +08:00
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return false;
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this->MF = &MF;
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TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
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OptForSize = MF.getFunction()->optForSize();
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MLI = &getAnalysis<MachineLoopInfo>();
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2016-12-08 08:15:51 +08:00
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LiveRegs.init(TII->getRegisterInfo());
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2016-02-12 03:43:04 +08:00
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DEBUG(dbgs() << "Start X86FixupBWInsts\n";);
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// Process all basic blocks.
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for (auto &MBB : MF)
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processBasicBlock(MF, MBB);
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DEBUG(dbgs() << "End X86FixupBWInsts\n";);
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return true;
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}
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// TODO: This method of analysis can miss some legal cases, because the
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// super-register could be live into the address expression for a memory
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// reference for the instruction, and still be killed/last used by the
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// instruction. However, the existing query interfaces don't seem to
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// easily allow that to be checked.
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//
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// What we'd really like to know is whether after OrigMI, the
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// only portion of SuperDestReg that is alive is the portion that
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// was the destination register of OrigMI.
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bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
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unsigned &SuperDestReg) const {
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2016-05-07 01:28:42 +08:00
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auto *TRI = &TII->getRegisterInfo();
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2016-02-12 03:43:04 +08:00
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unsigned OrigDestReg = OrigMI->getOperand(0).getReg();
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SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32);
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2016-05-07 01:28:42 +08:00
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const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
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2016-02-12 03:43:04 +08:00
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// Make sure that the sub-register that this instruction has as its
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// destination is the lowest order sub-register of the super-register.
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// If it isn't, then the register isn't really dead even if the
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// super-register is considered dead.
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2016-05-07 01:28:42 +08:00
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if (SubRegIdx == X86::sub_8bit_hi)
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2016-02-12 03:43:04 +08:00
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return false;
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2016-04-26 08:00:48 +08:00
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if (LiveRegs.contains(SuperDestReg))
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2016-02-12 03:43:04 +08:00
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return false;
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2016-05-07 01:28:42 +08:00
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if (SubRegIdx == X86::sub_8bit) {
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2016-02-12 03:43:04 +08:00
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// In the case of byte registers, we also have to check that the upper
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// byte register is also dead. That is considered to be independent of
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// whether the super-register is dead.
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2016-05-07 01:28:42 +08:00
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unsigned UpperByteReg =
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getX86SubSuperRegister(SuperDestReg, 8, /*High=*/true);
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2016-02-12 03:43:04 +08:00
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2016-04-26 08:00:48 +08:00
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if (LiveRegs.contains(UpperByteReg))
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2016-02-12 03:43:04 +08:00
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return false;
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}
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return true;
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}
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MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
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MachineInstr *MI) const {
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unsigned NewDestReg;
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// We are going to try to rewrite this load to a larger zero-extending
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// load. This is safe if all portions of the 32 bit super-register
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// of the original destination register, except for the original destination
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// register are dead. getSuperRegDestIfDead checks that.
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2016-05-07 01:28:42 +08:00
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if (!getSuperRegDestIfDead(MI, NewDestReg))
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2016-02-12 03:43:04 +08:00
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return nullptr;
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// Safe to change the instruction.
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MachineInstrBuilder MIB =
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BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
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unsigned NumArgs = MI->getNumOperands();
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for (unsigned i = 1; i < NumArgs; ++i)
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MIB.addOperand(MI->getOperand(i));
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MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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return MIB;
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}
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2016-05-07 09:11:17 +08:00
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MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
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assert(MI->getNumExplicitOperands() == 2);
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auto &OldDest = MI->getOperand(0);
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auto &OldSrc = MI->getOperand(1);
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unsigned NewDestReg;
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if (!getSuperRegDestIfDead(MI, NewDestReg))
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return nullptr;
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unsigned NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
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// This is only correct if we access the same subregister index: otherwise,
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// we could try to replace "movb %ah, %al" with "movl %eax, %eax".
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auto *TRI = &TII->getRegisterInfo();
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if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
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TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
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return nullptr;
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// Safe to change the instruction.
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// Don't set src flags, as we don't know if we're also killing the superreg.
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// However, the superregister might not be defined; make it explicit that
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// we don't care about the higher bits by reading it as Undef, and adding
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// an imp-use on the original subregister.
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MachineInstrBuilder MIB =
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BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
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.addReg(NewSrcReg, RegState::Undef)
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.addReg(OldSrc.getReg(), RegState::Implicit);
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// Drop imp-defs/uses that would be redundant with the new def/use.
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for (auto &Op : MI->implicit_operands())
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if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
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MIB.addOperand(Op);
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return MIB;
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}
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2016-06-16 00:03:06 +08:00
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MachineInstr *FixupBWInstPass::tryReplaceInstr(
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MachineInstr *MI, MachineBasicBlock &MBB,
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bool &WasCandidate) const {
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MachineInstr *NewMI = nullptr;
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WasCandidate = false;
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// See if this is an instruction of the type we are currently looking for.
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switch (MI->getOpcode()) {
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case X86::MOV8rm:
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// Only replace 8 bit loads with the zero extending versions if
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// in an inner most loop and not optimizing for size. This takes
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// an extra byte to encode, and provides limited performance upside.
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if (MachineLoop *ML = MLI->getLoopFor(&MBB)) {
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if (ML->begin() == ML->end() && !OptForSize) {
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NewMI = tryReplaceLoad(X86::MOVZX32rm8, MI);
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WasCandidate = true;
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}
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}
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break;
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case X86::MOV16rm:
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// Always try to replace 16 bit load with 32 bit zero extending.
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// Code size is the same, and there is sometimes a perf advantage
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// from eliminating a false dependence on the upper portion of
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// the register.
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NewMI = tryReplaceLoad(X86::MOVZX32rm16, MI);
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WasCandidate = true;
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break;
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case X86::MOV8rr:
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case X86::MOV16rr:
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// Always try to replace 8/16 bit copies with a 32 bit copy.
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// Code size is either less (16) or equal (8), and there is sometimes a
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// perf advantage from eliminating a false dependence on the upper portion
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// of the register.
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NewMI = tryReplaceCopy(MI);
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WasCandidate = true;
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break;
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default:
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// nothing to do here.
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break;
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}
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return NewMI;
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}
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2016-02-12 03:43:04 +08:00
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void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
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2016-04-26 08:00:48 +08:00
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MachineBasicBlock &MBB) {
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2016-02-12 03:43:04 +08:00
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// This algorithm doesn't delete the instructions it is replacing
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// right away. By leaving the existing instructions in place, the
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// register liveness information doesn't change, and this makes the
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// analysis that goes on be better than if the replaced instructions
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// were immediately removed.
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//
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// This algorithm always creates a replacement instruction
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// and notes that and the original in a data structure, until the
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// whole BB has been analyzed. This keeps the replacement instructions
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// from making it seem as if the larger register might be live.
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SmallVector<std::pair<MachineInstr *, MachineInstr *>, 8> MIReplacements;
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2016-04-26 08:00:48 +08:00
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// Start computing liveness for this block. We iterate from the end to be able
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// to update this for each instruction.
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LiveRegs.clear();
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2016-04-27 09:51:38 +08:00
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// We run after PEI, so we need to AddPristinesAndCSRs.
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2016-05-03 08:24:32 +08:00
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LiveRegs.addLiveOuts(MBB);
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2016-04-26 08:00:48 +08:00
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2016-06-16 00:03:06 +08:00
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bool WasCandidate = false;
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2016-04-26 08:00:48 +08:00
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for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
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MachineInstr *MI = &*I;
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2016-06-16 00:03:06 +08:00
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MachineInstr *NewMI = tryReplaceInstr(MI, MBB, WasCandidate);
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2016-02-12 03:43:04 +08:00
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2016-06-16 00:03:06 +08:00
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// Add this to replacements if it was a candidate, even if NewMI is
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// nullptr. We will revisit that in a bit.
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if (WasCandidate) {
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2016-02-12 03:43:04 +08:00
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MIReplacements.push_back(std::make_pair(MI, NewMI));
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2016-06-16 00:03:06 +08:00
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}
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2016-04-26 08:00:48 +08:00
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// We're done with this instruction, update liveness for the next one.
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LiveRegs.stepBackward(*MI);
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2016-02-12 03:43:04 +08:00
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}
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while (!MIReplacements.empty()) {
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MachineInstr *MI = MIReplacements.back().first;
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MachineInstr *NewMI = MIReplacements.back().second;
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MIReplacements.pop_back();
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2016-06-16 00:03:06 +08:00
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if (NewMI) {
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MBB.insert(MI, NewMI);
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MBB.erase(MI);
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}
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2016-02-12 03:43:04 +08:00
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}
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}
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