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llvm-project/llvm/test/MC/Mips/octeon-instructions.s

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[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=octeon | FileCheck %s
# CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28]
# CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28]
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
# CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
# CHECK: bbit0 $19, 22, foo # encoding: [0xca,0x76,A,A]
# CHECK: bbit032 $fp, 11, foo # encoding: [0xdb,0xcb,A,A]
[mips] Add range checks and transformation to octeon instructions in AsmParser. This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
2015-01-28 03:11:28 +08:00
# CHECK: bbit032 $8, 10, foo # encoding: [0xd9,0x0a,A,A]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
# CHECK: bbit1 $3, 31, foo # encoding: [0xe8,0x7f,A,A]
# CHECK: bbit132 $24, 10, foo # encoding: [0xfb,0x0a,A,A]
[mips] Add range checks and transformation to octeon instructions in AsmParser. This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
2015-01-28 03:11:28 +08:00
# CHECK: bbit132 $14, 14, foo # encoding: [0xf9,0xce,A,A]
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
# CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2]
# CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72]
# CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3]
# CHECK: cins32 $22, $22, 9, 22 # encoding: [0x72,0xd6,0xb2,0x73]
[mips] Add range checks and transformation to octeon instructions in AsmParser. This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
2015-01-28 03:11:28 +08:00
# CHECK: cins32 $24, $ra, 0, 31 # encoding: [0x73,0xf8,0xf8,0x33]
# CHECK: cins32 $15, $15, 5, 5 # encoding: [0x71,0xef,0x29,0x73]
[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
2015-05-29 00:23:16 +08:00
# CHECK: dmtc2 $2, 16455 # encoding: [0x48,0xa2,0x40,0x47]
# CHECK: dmfc2 $2, 64 # encoding: [0x48,0x22,0x00,0x40]
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
# CHECK: dmul $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x03]
# CHECK: dmul $19, $24, $25 # encoding: [0x73,0x19,0x98,0x03]
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03]
# CHECK: dmul $21, $21, $25 # encoding: [0x72,0xb9,0xa8,0x03]
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
# CHECK: dpop $9, $6 # encoding: [0x70,0xc0,0x48,0x2d]
# CHECK: dpop $15, $22 # encoding: [0x72,0xc0,0x78,0x2d]
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
# CHECK: dpop $12, $12 # encoding: [0x71,0x80,0x60,0x2d]
# CHECK: exts $4, $25, 27, 15 # encoding: [0x73,0x24,0x7e,0xfa]
# CHECK: exts $15, $15, 17, 6 # encoding: [0x71,0xef,0x34,0x7a]
# CHECK: exts32 $4, $13, 10, 8 # encoding: [0x71,0xa4,0x42,0xbb]
# CHECK: exts32 $15, $15, 11, 20 # encoding: [0x71,0xef,0xa2,0xfb]
[mips] Add range checks and transformation to octeon instructions in AsmParser. This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
2015-01-28 03:11:28 +08:00
# CHECK: exts32 $7, $4, 22, 9 # encoding: [0x70,0x87,0x4d,0xbb]
# CHECK: exts32 $25, $25, 5, 25 # encoding: [0x73,0x39,0xc9,0x7b]
[mips] Add Octeon cnMips instructions mtmX and mtpX Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px". Includes tests. Reviews by: Daniel.Sanders@imgtec.com llvm-svn: 205343
2014-04-02 02:35:26 +08:00
# CHECK: mtm0 $15 # encoding: [0x71,0xe0,0x00,0x08]
# CHECK: mtm1 $16 # encoding: [0x72,0x00,0x00,0x0c]
# CHECK: mtm2 $17 # encoding: [0x72,0x20,0x00,0x0d]
# CHECK: mtp0 $18 # encoding: [0x72,0x40,0x00,0x09]
# CHECK: mtp1 $19 # encoding: [0x72,0x60,0x00,0x0a]
# CHECK: mtp2 $20 # encoding: [0x72,0x80,0x00,0x0b]
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
# CHECK: pop $9, $6 # encoding: [0x70,0xc0,0x48,0x2c]
# CHECK: pop $8, $19 # encoding: [0x72,0x60,0x40,0x2c]
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
# CHECK: pop $2, $2 # encoding: [0x70,0x40,0x10,0x2c]
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
# CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a]
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
# CHECK: seq $6, $6, $24 # encoding: [0x70,0xd8,0x30,0x2a]
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
# CHECK: seqi $17, $15, -512 # encoding: [0x71,0xf1,0x80,0x2e]
# CHECK: seqi $16, $16, 38 # encoding: [0x72,0x10,0x09,0xae]
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
# CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b]
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
# CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b]
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
# CHECK: snei $4, $16, -313 # encoding: [0x72,0x04,0xb1,0xef]
# CHECK: snei $26, $26, 511 # encoding: [0x73,0x5a,0x7f,0xef]
[MIPS] Add aliases for sync instruction used by Octeon CPU This commit adds aliases for the sync instruction (synciobdma, syncs, syncw, syncws) which are used by the Octeon CPU. Reviewed by D. Sanders llvm-svn: 217477
2014-09-10 14:10:24 +08:00
# CHECK: sync 2 # encoding: [0x00,0x00,0x00,0x8f]
# CHECK: sync 6 # encoding: [0x00,0x00,0x01,0x8f]
# CHECK: sync 4 # encoding: [0x00,0x00,0x01,0x0f]
# CHECK: sync 5 # encoding: [0x00,0x00,0x01,0x4f]
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
# CHECK: v3mulu $21, $10, $21 # encoding: [0x71,0x55,0xa8,0x11]
# CHECK: v3mulu $20, $20, $10 # encoding: [0x72,0x8a,0xa0,0x11]
# CHECK: vmm0 $3, $19, $16 # encoding: [0x72,0x70,0x18,0x10]
# CHECK: vmm0 $ra, $ra, $9 # encoding: [0x73,0xe9,0xf8,0x10]
# CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f]
# CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f]
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
foo:
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
baddu $9, $6, $7
baddu $17, $18, $19
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
baddu $2, $3
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
bbit0 $19, 22, foo
bbit032 $30, 11, foo
[mips] Add range checks and transformation to octeon instructions in AsmParser. This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
2015-01-28 03:11:28 +08:00
bbit0 $8, 42, foo
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-21 00:10:51 +08:00
bbit1 $3, 31, foo
bbit132 $24, 10, foo
[mips] Add range checks and transformation to octeon instructions in AsmParser. This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
2015-01-28 03:11:28 +08:00
bbit1 $14, 46, foo
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
cins $25, $10, 22, 2
cins $9, 17, 29
cins32 $15, $2, 18, 8
cins32 $22, 9, 22
[mips] Add range checks and transformation to octeon instructions in AsmParser. This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
2015-01-28 03:11:28 +08:00
cins $24, $31, 32, 31
cins $15, 37, 5
[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
2015-05-29 00:23:16 +08:00
dmtc2 $2, 0x4047
dmfc2 $2, 0x0040
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
dmul $9, $6, $7
dmul $19, $24, $25
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
dmul $9, $6
dmul $21, $25
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
dpop $9, $6
dpop $15, $22
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
dpop $12
exts $4, $25, 27, 15
exts $15, 17, 6
exts32 $4, $13, 10, 8
exts32 $15, 11, 20
[mips] Add range checks and transformation to octeon instructions in AsmParser. This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
2015-01-28 03:11:28 +08:00
exts $7, $4, 54, 9
exts $25, 37, 25
[mips] Add Octeon cnMips instructions mtmX and mtpX Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px". Includes tests. Reviews by: Daniel.Sanders@imgtec.com llvm-svn: 205343
2014-04-02 02:35:26 +08:00
mtm0 $15
mtm1 $16
mtm2 $17
mtp0 $18
mtp1 $19
mtp2 $20
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
pop $9, $6
pop $8, $19
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
pop $2
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
seq $25, $23, $24
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
seq $6, $24
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
seqi $17, $15, -512
seqi $16, 38
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
sne $25, $23, $24
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
sne $23, $20
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
snei $4, $16, -313
snei $26, 511
[MIPS] Add aliases for sync instruction used by Octeon CPU This commit adds aliases for the sync instruction (synciobdma, syncs, syncw, syncws) which are used by the Octeon CPU. Reviewed by D. Sanders llvm-svn: 217477
2014-09-10 14:10:24 +08:00
synciobdma
syncs
syncw
syncws
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
v3mulu $21, $10, $21
v3mulu $20, $10
vmm0 $3, $19, $16
vmm0 $31, $9
vmulu $29, $10, $17
vmulu $27, $6