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llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td

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WebAssembly: basic instructions todo, and basic register info. Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
2015-07-11 02:23:10 +08:00
// WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
///
/// \file
/// \brief WebAssembly Memory operand code-gen constructs.
///
//===----------------------------------------------------------------------===//
[WebAssembly] Clean up several FIXME comments. llvm-svn: 254079
2015-11-26 02:13:18 +08:00
// TODO:
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// - HasAddr64
// - WebAssemblyTargetLowering having to do with atomics
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// - Each has optional alignment.
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
// local types. These memory-only types instead zero- or sign-extend into local
// types when loading, and truncate when storing.
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// WebAssembly constant offsets are performed as unsigned with infinite
// precision, so we need to check for NoUnsignedWrap so that we don't fold an
// offset for an add that needs wrapping.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def regPlusImm : PatFrag<(ops node:$addr, node:$off),
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
(add node:$addr, node:$off),
[{ return N->getFlags()->hasNoUnsignedWrap(); }]>;
[WebAssembly] Teach address folding to fold bitwise-or nodes. LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
2016-02-23 04:04:02 +08:00
// Treat an 'or' node as an 'add' if the or'ed bits are known to be zero.
def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
APInt KnownZero0, KnownOne0;
CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
APInt KnownZero1, KnownOne1;
CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
return (~KnownZero0 & ~KnownZero1) == 0;
}]>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
// GlobalAddresses are conceptually unsigned values, so we can also fold them
[WebAssembly] Disable folding of GA+reg into load/store constant offsets Summary: If the register has a negative value then unsigned overflow will occur; this case is sometimes even created intentionally by LSR. For now disable GA+reg folding. Fixes PR29127 Differential Revision: https://reviews.llvm.org/D24053 llvm-svn: 280285
2016-09-01 04:27:20 +08:00
// into immediate values as long as the add is 'nuw'.
// TODO: We'd like to also match GA offsets but there are cases where the
// register can have a negative value. Find out what more we can do.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def regPlusGA : PatFrag<(ops node:$addr, node:$off),
(add node:$addr, node:$off),
[{
[WebAssembly] Disable folding of GA+reg into load/store constant offsets Summary: If the register has a negative value then unsigned overflow will occur; this case is sometimes even created intentionally by LSR. For now disable GA+reg folding. Fixes PR29127 Differential Revision: https://reviews.llvm.org/D24053 llvm-svn: 280285
2016-09-01 04:27:20 +08:00
return N->getFlags()->hasNoUnsignedWrap();
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
}]>;
// We don't need a regPlusES because external symbols never have constant
// offsets folded into them, so we can just use add.
[WebAssembly] Use a physical register to describe ARGUMENT liveness. Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
2015-11-26 03:36:19 +08:00
let Defs = [ARGUMENTS] in {
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// Basic load.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i32.load\t$dst, ${off}(${addr})${p2align}", 0x2a>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i64.load\t$dst, ${off}(${addr})${p2align}", 0x2b>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"f32.load\t$dst, ${off}(${addr})${p2align}", 0x2c>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"f64.load\t$dst, ${off}(${addr})${p2align}", 0x2d>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
} // Defs = [ARGUMENTS]
// Select loads with no constant offset.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr, 0)>;
def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr, 0)>;
def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr, 0)>;
def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr, 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select loads with a constant offset.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I32 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(f32 (load (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F32 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(f64 (load (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F64 imm:$off, $addr, 0)>;
[WebAssembly] Teach address folding to fold bitwise-or nodes. LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
2016-02-23 04:04:02 +08:00
def : Pat<(i32 (load (or_is_add I32:$addr, imm:$off))),
(LOAD_I32 imm:$off, $addr, 0)>;
def : Pat<(i64 (load (or_is_add I32:$addr, imm:$off))),
(LOAD_I64 imm:$off, $addr, 0)>;
def : Pat<(f32 (load (or_is_add I32:$addr, imm:$off))),
(LOAD_F32 imm:$off, $addr, 0)>;
def : Pat<(f64 (load (or_is_add I32:$addr, imm:$off))),
(LOAD_F64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (load (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I32 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (load (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(f32 (load (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F32 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(f64 (load (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (load (add I32:$addr, (WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I32 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (load (add I32:$addr, (WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(f32 (load (add I32:$addr, (WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F32 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(f64 (load (add I32:$addr, (WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select loads with just a constant offset.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def : Pat<(i32 (load imm:$off)), (LOAD_I32 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (load imm:$off)), (LOAD_I64 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(f32 (load imm:$off)), (LOAD_F32 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(f64 (load imm:$off)), (LOAD_F64 imm:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (load (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I32 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (load (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(f32 (load (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F32 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(f64 (load (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (load (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I32 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (load (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(f32 (load (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F32 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(f64 (load (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD_F64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
let Defs = [ARGUMENTS] in {
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// Extending load.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD8_S_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i32.load8_s\t$dst, ${off}(${addr})${p2align}", 0x20>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD8_U_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i32.load8_u\t$dst, ${off}(${addr})${p2align}", 0x21>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD16_S_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i32.load16_s\t$dst, ${off}(${addr})${p2align}", 0x22>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD16_U_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i32.load16_u\t$dst, ${off}(${addr})${p2align}", 0x23>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD8_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i64.load8_s\t$dst, ${off}(${addr})${p2align}", 0x24>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD8_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i64.load8_u\t$dst, ${off}(${addr})${p2align}", 0x25>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD16_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i64.load16_s\t$dst, ${off}(${addr})${p2align}", 0x26>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD16_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i64.load16_u\t$dst, ${off}(${addr})${p2align}", 0x27>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD32_S_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i64.load32_s\t$dst, ${off}(${addr})${p2align}", 0x28>;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def LOAD32_U_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
P2Align:$p2align), [],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"i64.load32_u\t$dst, ${off}(${addr})${p2align}", 0x29>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
[WebAssembly] Use a physical register to describe ARGUMENT liveness. Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
2015-11-26 03:36:19 +08:00
} // Defs = [ARGUMENTS]
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
// Select extending loads with no constant offset.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def : Pat<(i32 (sextloadi8 I32:$addr)), (LOAD8_S_I32 0, $addr, 0)>;
def : Pat<(i32 (zextloadi8 I32:$addr)), (LOAD8_U_I32 0, $addr, 0)>;
def : Pat<(i32 (sextloadi16 I32:$addr)), (LOAD16_S_I32 0, $addr, 0)>;
def : Pat<(i32 (zextloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr, 0)>;
def : Pat<(i64 (sextloadi8 I32:$addr)), (LOAD8_S_I64 0, $addr, 0)>;
def : Pat<(i64 (zextloadi8 I32:$addr)), (LOAD8_U_I64 0, $addr, 0)>;
def : Pat<(i64 (sextloadi16 I32:$addr)), (LOAD16_S_I64 0, $addr, 0)>;
def : Pat<(i64 (zextloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr, 0)>;
def : Pat<(i64 (sextloadi32 I32:$addr)), (LOAD32_S_I64 0, $addr, 0)>;
def : Pat<(i64 (zextloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr, 0)>;
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select extending loads with a constant offset.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (sextloadi8 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I32 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (zextloadi8 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (sextloadi16 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I32 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (zextloadi16 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi8 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi8 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi16 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi16 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi32 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_S_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi32 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 imm:$off, $addr, 0)>;
[WebAssembly] Teach address folding to fold bitwise-or nodes. LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
2016-02-23 04:04:02 +08:00
def : Pat<(i32 (sextloadi8 (or_is_add I32:$addr, imm:$off))),
(LOAD8_S_I32 imm:$off, $addr, 0)>;
def : Pat<(i32 (zextloadi8 (or_is_add I32:$addr, imm:$off))),
(LOAD8_U_I32 imm:$off, $addr, 0)>;
def : Pat<(i32 (sextloadi16 (or_is_add I32:$addr, imm:$off))),
(LOAD16_S_I32 imm:$off, $addr, 0)>;
def : Pat<(i32 (zextloadi16 (or_is_add I32:$addr, imm:$off))),
(LOAD16_U_I32 imm:$off, $addr, 0)>;
def : Pat<(i64 (sextloadi8 (or_is_add I32:$addr, imm:$off))),
(LOAD8_S_I64 imm:$off, $addr, 0)>;
def : Pat<(i64 (zextloadi8 (or_is_add I32:$addr, imm:$off))),
(LOAD8_U_I64 imm:$off, $addr, 0)>;
def : Pat<(i64 (sextloadi16 (or_is_add I32:$addr, imm:$off))),
(LOAD16_S_I64 imm:$off, $addr, 0)>;
def : Pat<(i64 (zextloadi16 (or_is_add I32:$addr, imm:$off))),
(LOAD16_U_I64 imm:$off, $addr, 0)>;
def : Pat<(i64 (sextloadi32 (or_is_add I32:$addr, imm:$off))),
(LOAD32_S_I64 imm:$off, $addr, 0)>;
def : Pat<(i64 (zextloadi32 (or_is_add I32:$addr, imm:$off))),
(LOAD32_U_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (sextloadi8 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I32 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (zextloadi8 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (sextloadi16 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I32 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (zextloadi16 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi8 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi8 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi16 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi16 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi32 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_S_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi32 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (sextloadi8 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I32 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (zextloadi8 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (sextloadi16 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I32 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (zextloadi16 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi8 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi8 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi16 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi16 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (sextloadi32 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_S_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (zextloadi32 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select extending loads with just a constant offset.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def : Pat<(i32 (sextloadi8 imm:$off)),
(LOAD8_S_I32 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i32 (zextloadi8 imm:$off)),
(LOAD8_U_I32 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i32 (sextloadi16 imm:$off)),
(LOAD16_S_I32 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i32 (zextloadi16 imm:$off)),
(LOAD16_U_I32 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (sextloadi8 imm:$off)),
(LOAD8_S_I64 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (zextloadi8 imm:$off)),
(LOAD8_U_I64 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (sextloadi16 imm:$off)),
(LOAD16_S_I64 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (zextloadi16 imm:$off)),
(LOAD16_U_I64 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (sextloadi32 imm:$off)),
(LOAD32_S_I64 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (zextloadi32 imm:$off)),
(LOAD32_U_I64 imm:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (sextloadi8 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I32 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (zextloadi8 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (sextloadi16 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I32 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (zextloadi16 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (sextloadi8 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (zextloadi8 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (sextloadi16 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (zextloadi16 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (sextloadi32 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_S_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (zextloadi32 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (sextloadi8 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I32 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (zextloadi8 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (sextloadi16 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I32 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (zextloadi16 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (sextloadi8 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_S_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (zextloadi8 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (sextloadi16 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_S_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (zextloadi16 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (sextloadi32 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_S_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (zextloadi32 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Resolve "don't care" extending loads to zero-extending loads. This is
// somewhat arbitrary, but zero-extending is conceptually simpler.
// Select "don't care" extending loads with no constant offset.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 0, $addr, 0)>;
def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 0, $addr, 0)>;
def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 0, $addr, 0)>;
def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 0, $addr, 0)>;
def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 0, $addr, 0)>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select "don't care" extending loads with a constant offset.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (extloadi8 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (extloadi16 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi8 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi16 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi32 (regPlusImm I32:$addr, imm:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 imm:$off, $addr, 0)>;
[WebAssembly] Teach address folding to fold bitwise-or nodes. LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
2016-02-23 04:04:02 +08:00
def : Pat<(i32 (extloadi8 (or_is_add I32:$addr, imm:$off))),
(LOAD8_U_I32 imm:$off, $addr, 0)>;
def : Pat<(i32 (extloadi16 (or_is_add I32:$addr, imm:$off))),
(LOAD16_U_I32 imm:$off, $addr, 0)>;
def : Pat<(i64 (extloadi8 (or_is_add I32:$addr, imm:$off))),
(LOAD8_U_I64 imm:$off, $addr, 0)>;
def : Pat<(i64 (extloadi16 (or_is_add I32:$addr, imm:$off))),
(LOAD16_U_I64 imm:$off, $addr, 0)>;
def : Pat<(i64 (extloadi32 (or_is_add I32:$addr, imm:$off))),
(LOAD32_U_I64 imm:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (extloadi8 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (extloadi16 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi8 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi16 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi32 (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 tglobaladdr:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (extloadi8 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i32 (extloadi16 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi8 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi16 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(i64 (extloadi32 (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 texternalsym:$off, $addr, 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select "don't care" extending loads with just a constant offset.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def : Pat<(i32 (extloadi8 imm:$off)),
(LOAD8_U_I32 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i32 (extloadi16 imm:$off)),
(LOAD16_U_I32 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (extloadi8 imm:$off)),
(LOAD8_U_I64 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (extloadi16 imm:$off)),
(LOAD16_U_I64 imm:$off, (CONST_I32 0), 0)>;
def : Pat<(i64 (extloadi32 imm:$off)),
(LOAD32_U_I64 imm:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (extloadi8 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (extloadi16 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (extloadi8 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (extloadi16 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (extloadi32 (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (extloadi8 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I32 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i32 (extloadi16 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I32 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (extloadi8 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD8_U_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (extloadi16 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD16_U_I64 texternalsym:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(i64 (extloadi32 (WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(LOAD32_U_I64 tglobaladdr:$off, (CONST_I32 0), 0)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
[WebAssembly] Use a physical register to describe ARGUMENT liveness. Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
2015-11-26 03:36:19 +08:00
let Defs = [ARGUMENTS] in {
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// Basic store.
// Note: WebAssembly inverts SelectionDAG's usual operand order.
[WebAssembly] Remove the output operand from stores. Per spec changes, store instructions in WebAssembly no longer have a return value. Update the instruction descriptions. Differential Revision: https://reviews.llvm.org/D25122 llvm-svn: 283501
2016-10-07 06:08:28 +08:00
def STORE_I32 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, I32:$val), [],
"i32.store\t${off}(${addr})${p2align}, $val", 0x33>;
def STORE_I64 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, I64:$val), [],
"i64.store\t${off}(${addr})${p2align}, $val", 0x34>;
def STORE_F32 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, F32:$val), [],
"f32.store\t${off}(${addr})${p2align}, $val", 0x35>;
def STORE_F64 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, F64:$val), [],
"f64.store\t${off}(${addr})${p2align}, $val", 0x36>;
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
[WebAssembly] Use a physical register to describe ARGUMENT liveness. Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
2015-11-26 03:36:19 +08:00
} // Defs = [ARGUMENTS]
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select stores with no constant offset.
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
def : Pat<(store I32:$val, I32:$addr), (STORE_I32 0, I32:$addr, 0, I32:$val)>;
def : Pat<(store I64:$val, I32:$addr), (STORE_I64 0, I32:$addr, 0, I64:$val)>;
def : Pat<(store F32:$val, I32:$addr), (STORE_F32 0, I32:$addr, 0, F32:$val)>;
def : Pat<(store F64:$val, I32:$addr), (STORE_F64 0, I32:$addr, 0, F64:$val)>;
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select stores with a constant offset.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store I32:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I32 imm:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store I64:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I64 imm:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store F32:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F32 imm:$off, I32:$addr, 0, F32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store F64:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F64 imm:$off, I32:$addr, 0, F64:$val)>;
[WebAssembly] Teach address folding to fold bitwise-or nodes. LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
2016-02-23 04:04:02 +08:00
def : Pat<(store I32:$val, (or_is_add I32:$addr, imm:$off)),
(STORE_I32 imm:$off, I32:$addr, 0, I32:$val)>;
def : Pat<(store I64:$val, (or_is_add I32:$addr, imm:$off)),
(STORE_I64 imm:$off, I32:$addr, 0, I64:$val)>;
def : Pat<(store F32:$val, (or_is_add I32:$addr, imm:$off)),
(STORE_F32 imm:$off, I32:$addr, 0, F32:$val)>;
def : Pat<(store F64:$val, (or_is_add I32:$addr, imm:$off)),
(STORE_F64 imm:$off, I32:$addr, 0, F64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store I32:$val, (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I32 tglobaladdr:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store I64:$val, (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I64 tglobaladdr:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store F32:$val, (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F32 tglobaladdr:$off, I32:$addr, 0, F32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store F64:$val, (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F64 tglobaladdr:$off, I32:$addr, 0, F64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store I32:$val, (add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I32 texternalsym:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store I64:$val, (add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I64 texternalsym:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store F32:$val, (add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F32 texternalsym:$off, I32:$addr, 0, F32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(store F64:$val, (add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F64 texternalsym:$off, I32:$addr, 0, F64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select stores with just a constant offset.
def : Pat<(store I32:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I32 imm:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store I64:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I64 imm:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store F32:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F32 imm:$off, (CONST_I32 0), 0, F32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store F64:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F64 imm:$off, (CONST_I32 0), 0, F64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store I32:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I32 tglobaladdr:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store I64:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I64 tglobaladdr:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store F32:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F32 tglobaladdr:$off, (CONST_I32 0), 0, F32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store F64:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F64 tglobaladdr:$off, (CONST_I32 0), 0, F64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store I32:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I32 texternalsym:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store I64:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_I64 texternalsym:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store F32:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F32 texternalsym:$off, (CONST_I32 0), 0, F32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(store F64:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE_F64 texternalsym:$off, (CONST_I32 0), 0, F64:$val)>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
[WebAssembly] Use a physical register to describe ARGUMENT liveness. Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
2015-11-26 03:36:19 +08:00
let Defs = [ARGUMENTS] in {
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// Truncating store.
[WebAssembly] Remove the output operand from stores. Per spec changes, store instructions in WebAssembly no longer have a return value. Update the instruction descriptions. Differential Revision: https://reviews.llvm.org/D25122 llvm-svn: 283501
2016-10-07 06:08:28 +08:00
def STORE8_I32 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, I32:$val), [],
"i32.store8\t${off}(${addr})${p2align}, $val", 0x2e>;
def STORE16_I32 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, I32:$val), [],
"i32.store16\t${off}(${addr})${p2align}, $val", 0x2f>;
def STORE8_I64 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, I64:$val), [],
"i64.store8\t${off}(${addr})${p2align}, $val", 0x30>;
def STORE16_I64 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, I64:$val), [],
"i64.store16\t${off}(${addr})${p2align}, $val", 0x31>;
def STORE32_I64 : I<(outs), (ins i32imm:$off, I32:$addr,
P2Align:$p2align, I64:$val), [],
"i64.store32\t${off}(${addr})${p2align}, $val", 0x32>;
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
[WebAssembly] Use a physical register to describe ARGUMENT liveness. Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
2015-11-26 03:36:19 +08:00
} // Defs = [ARGUMENTS]
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select truncating stores with no constant offset.
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
def : Pat<(truncstorei8 I32:$val, I32:$addr),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I32 0, I32:$addr, 0, I32:$val)>;
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
def : Pat<(truncstorei16 I32:$val, I32:$addr),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I32 0, I32:$addr, 0, I32:$val)>;
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
def : Pat<(truncstorei8 I64:$val, I32:$addr),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I64 0, I32:$addr, 0, I64:$val)>;
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
def : Pat<(truncstorei16 I64:$val, I32:$addr),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I64 0, I32:$addr, 0, I64:$val)>;
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
def : Pat<(truncstorei32 I64:$val, I32:$addr),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE32_I64 0, I32:$addr, 0, I64:$val)>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select truncating stores with a constant offset.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei8 I32:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I32 imm:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei16 I32:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I32 imm:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei8 I64:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I64 imm:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei16 I64:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I64 imm:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei32 I64:$val, (regPlusImm I32:$addr, imm:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE32_I64 imm:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Teach address folding to fold bitwise-or nodes. LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
2016-02-23 04:04:02 +08:00
def : Pat<(truncstorei8 I32:$val, (or_is_add I32:$addr, imm:$off)),
(STORE8_I32 imm:$off, I32:$addr, 0, I32:$val)>;
def : Pat<(truncstorei16 I32:$val, (or_is_add I32:$addr, imm:$off)),
(STORE16_I32 imm:$off, I32:$addr, 0, I32:$val)>;
def : Pat<(truncstorei8 I64:$val, (or_is_add I32:$addr, imm:$off)),
(STORE8_I64 imm:$off, I32:$addr, 0, I64:$val)>;
def : Pat<(truncstorei16 I64:$val, (or_is_add I32:$addr, imm:$off)),
(STORE16_I64 imm:$off, I32:$addr, 0, I64:$val)>;
def : Pat<(truncstorei32 I64:$val, (or_is_add I32:$addr, imm:$off)),
(STORE32_I64 imm:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei8 I32:$val,
(regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I32 tglobaladdr:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei16 I32:$val,
(regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I32 tglobaladdr:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei8 I64:$val,
(regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I64 tglobaladdr:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei16 I64:$val,
(regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I64 tglobaladdr:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei32 I64:$val,
(regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE32_I64 tglobaladdr:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei8 I32:$val, (add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I32 texternalsym:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei16 I32:$val,
(add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I32 texternalsym:$off, I32:$addr, 0, I32:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei8 I64:$val,
(add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I64 texternalsym:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei16 I64:$val,
(add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I64 texternalsym:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def : Pat<(truncstorei32 I64:$val,
(add I32:$addr,
(WebAssemblywrapper texternalsym:$off))),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE32_I64 texternalsym:$off, I32:$addr, 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select truncating stores with just a constant offset.
def : Pat<(truncstorei8 I32:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I32 imm:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei16 I32:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I32 imm:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei8 I64:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I64 imm:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei16 I64:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I64 imm:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei32 I64:$val, imm:$off),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE32_I64 imm:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei8 I32:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I32 tglobaladdr:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei16 I32:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I32 tglobaladdr:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei8 I64:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I64 tglobaladdr:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei16 I64:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I64 tglobaladdr:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei32 I64:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE32_I64 tglobaladdr:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei8 I32:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I32 texternalsym:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei16 I32:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I32 texternalsym:$off, (CONST_I32 0), 0, I32:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei8 I64:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE8_I64 texternalsym:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei16 I64:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE16_I64 texternalsym:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
def : Pat<(truncstorei32 I64:$val, (WebAssemblywrapper texternalsym:$off)),
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
(STORE32_I64 texternalsym:$off, (CONST_I32 0), 0, I64:$val)>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
[WebAssembly] Use a physical register to describe ARGUMENT liveness. Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
2015-11-26 03:36:19 +08:00
let Defs = [ARGUMENTS] in {
[WebAssembly] Rename memory_size intrinsic to current_memory This follows the recent renaming in the wasm spec. llvm-svn: 268255
2016-05-03 01:25:22 +08:00
// Current memory size.
def CURRENT_MEMORY_I32 : I<(outs I32:$dst), (ins),
[(set I32:$dst, (int_wasm_current_memory))],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"current_memory\t$dst", 0x3b>,
[WebAssembly] Rename memory_size intrinsic to current_memory This follows the recent renaming in the wasm spec. llvm-svn: 268255
2016-05-03 01:25:22 +08:00
Requires<[HasAddr32]>;
def CURRENT_MEMORY_I64 : I<(outs I64:$dst), (ins),
[(set I64:$dst, (int_wasm_current_memory))],
"current_memory\t$dst">,
Requires<[HasAddr64]>;
[WebAssembly] Add a resize_memory intrinsic. llvm-svn: 249178
2015-10-03 04:10:26 +08:00
[WebAssembly] Update wasm builtin functions to match spec changes. The page_size operator has been removed from the spec, and the resize_memory operator has been changed to grow_memory. llvm-svn: 252202
2015-11-06 04:16:59 +08:00
// Grow memory.
[WebAssembly] Rename memory intrinsics to be upper-case, following convention. NFC. llvm-svn: 253070
2015-11-14 04:19:11 +08:00
def GROW_MEMORY_I32 : I<(outs), (ins I32:$delta),
[WebAssembly] Add AsmString strings for most instructions. Mangling type information into MachineInstr opcode names was a temporary measure, and it's starting to get hairy. At the same time, the MC instruction printer wants to use AsmString strings for printing. This patch takes the first step, starting the process of adding AsmStrings for instructions. llvm-svn: 252203
2015-11-06 04:42:30 +08:00
[(int_wasm_grow_memory I32:$delta)],
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
"grow_memory\t$delta", 0x39>,
[WebAssembly] Update wasm builtin functions to match spec changes. The page_size operator has been removed from the spec, and the resize_memory operator has been changed to grow_memory. llvm-svn: 252202
2015-11-06 04:16:59 +08:00
Requires<[HasAddr32]>;
[WebAssembly] Rename memory intrinsics to be upper-case, following convention. NFC. llvm-svn: 253070
2015-11-14 04:19:11 +08:00
def GROW_MEMORY_I64 : I<(outs), (ins I64:$delta),
[WebAssembly] Add AsmString strings for most instructions. Mangling type information into MachineInstr opcode names was a temporary measure, and it's starting to get hairy. At the same time, the MC instruction printer wants to use AsmString strings for printing. This patch takes the first step, starting the process of adding AsmStrings for instructions. llvm-svn: 252203
2015-11-06 04:42:30 +08:00
[(int_wasm_grow_memory I64:$delta)],
[WebAssembly] Don't print the types of memory_size and grow_memory This matches the current spec, for now. llvm-svn: 253931
2015-11-24 06:37:29 +08:00
"grow_memory\t$delta">,
[WebAssembly] Update wasm builtin functions to match spec changes. The page_size operator has been removed from the spec, and the resize_memory operator has been changed to grow_memory. llvm-svn: 252202
2015-11-06 04:16:59 +08:00
Requires<[HasAddr64]>;
[WebAssembly] Use a physical register to describe ARGUMENT liveness. Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
2015-11-26 03:36:19 +08:00
} // Defs = [ARGUMENTS]