2012-05-11 05:48:22 +08:00
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; Positive test for inline register constraints
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;
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2012-07-06 07:58:21 +08:00
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=LITTLE
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; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=BIG
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2012-05-11 05:48:22 +08:00
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2012-07-06 07:58:21 +08:00
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%union.u_tag = type { i64 }
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%struct.anon = type { i32, i32 }
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@uval = common global %union.u_tag zeroinitializer, align 8
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2012-05-11 05:48:22 +08:00
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define i32 @main() nounwind {
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entry:
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; X with -3
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2012-07-06 07:58:21 +08:00
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;LITTLE: #APP
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;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
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;LITTLE: #NO_APP
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2012-05-11 05:48:22 +08:00
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tail call i32 asm sideeffect "addi $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) nounwind
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2012-05-19 01:39:35 +08:00
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; x with -3
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2012-07-06 07:58:21 +08:00
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;LITTLE: #APP
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;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},0xfffd
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;LITTLE: #NO_APP
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2012-05-19 01:39:35 +08:00
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tail call i32 asm sideeffect "addi $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) nounwind
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2012-05-19 08:51:56 +08:00
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; d with -3
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2012-07-06 07:58:21 +08:00
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;LITTLE: #APP
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;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},-3
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;LITTLE: #NO_APP
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2012-05-19 08:51:56 +08:00
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tail call i32 asm sideeffect "addi $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) nounwind
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2012-05-31 03:05:19 +08:00
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; m with -3
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2012-07-06 07:58:21 +08:00
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;LITTLE: #APP
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;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},-4
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;LITTLE: #NO_APP
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2012-05-31 03:05:19 +08:00
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tail call i32 asm sideeffect "addi $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) nounwind
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2012-06-28 09:33:40 +08:00
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; z with -3
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2012-07-06 07:58:21 +08:00
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;LITTLE: #APP
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;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},-3
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;LITTLE: #NO_APP
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2012-06-28 09:33:40 +08:00
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tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) nounwind
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; z with 0
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2012-07-06 07:58:21 +08:00
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;LITTLE: #APP
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;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},$0
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;LITTLE: #NO_APP
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2012-06-28 09:33:40 +08:00
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tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
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2012-07-03 07:35:23 +08:00
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; a long long in 32 bit mode (use to assert)
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2012-07-06 07:58:21 +08:00
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;LITTLE: #APP
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;LITTLE: addi ${{[0-9]+}},${{[0-9]+}},3
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;LITTLE: #NO_APP
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2012-07-03 07:35:23 +08:00
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tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
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2012-07-06 07:58:21 +08:00
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; D, in little endian the source reg will be 4 bytes into the long long
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;LITTLE: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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;LITTLE: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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;LITTLE-NEXT: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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;LITTLE: #APP
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Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
llvm-svn: 160028
2012-07-11 06:41:20 +08:00
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;LITTLE: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
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2012-07-06 07:58:21 +08:00
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;LITTLE: #NO_APP
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; D, in big endian the source reg will also be 4 bytes into the long long
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;BIG: #APP
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;BIG: #APP
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;BIG: #APP
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;BIG: #APP
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;BIG: #APP
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;BIG: #APP
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;BIG: #APP
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;BIG: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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;BIG: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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;BIG-NEXT: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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;BIG: #APP
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;BIG: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
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;BIG: #NO_APP
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%7 = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8
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%trunc1 = trunc i64 %7 to i32
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tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %7, i32 %trunc1) nounwind
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Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
llvm-svn: 160028
2012-07-11 06:41:20 +08:00
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; L, in little endian the source reg will be 4 bytes into the long long
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;LITTLE: #APP
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;LITTLE: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
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;LITTLE: #NO_APP
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; L, in big endian the source reg will be 0 bytes into the long long
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;BIG: #APP
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;BIG: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
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;BIG: #NO_APP
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tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %7, i32 %trunc1) nounwind
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2012-05-11 05:48:22 +08:00
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ret i32 0
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}
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2012-07-06 07:58:21 +08:00
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