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llvm-project/llvm/test/CodeGen/X86/legalize-shl-vec.ll

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Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
; RUN: llc < %s -march=x86-64 | FileCheck %s
define <2 x i256> @test_shl(<2 x i256> %In) {
%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
%Out = shl <2 x i256> %In, %Amt
ret <2 x i256> %Out
; CHECK-LABEL: test_shl
; CHECK: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK: retq
}
define <2 x i256> @test_srl(<2 x i256> %In) {
%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
%Out = lshr <2 x i256> %In, %Amt
ret <2 x i256> %Out
; CHECK-LABEL: test_srl
; CHECK: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK-NEXT: movq $0
; CHECK: retq
}
define <2 x i256> @test_sra(<2 x i256> %In) {
%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
%Out = ashr <2 x i256> %In, %Amt
ret <2 x i256> %Out
; CHECK-LABEL: test_sra
; CHECK: sarq $63
}