2017-10-19 07:18:12 +08:00
|
|
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
2017-03-16 00:51:41 +08:00
|
|
|
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
|
|
|
|
|
|
|
--- |
|
|
|
|
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
|
|
|
|
|
|
|
|
define i32 @const_s32() { ret i32 42 }
|
|
|
|
define i64 @const_s64() { ret i64 1234567890123 }
|
|
|
|
|
|
|
|
define i32 @fconst_s32() { ret i32 42 }
|
|
|
|
define i64 @fconst_s64() { ret i64 1234567890123 }
|
[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf.
Summary:
There's only a tablegen testcase for IntImmLeaf and not a CodeGen one
because the relevant rules are rejected for other reasons at the moment.
On AArch64, it's because there's an SDNodeXForm attached to the operand.
On X86, it's because the rule either emits multiple instructions or has
another predicate using PatFrag which cannot easily be supported at the
same time.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36569
llvm-svn: 315761
2017-10-14 05:28:03 +08:00
|
|
|
define float @fconst_s32_0() { ret float 0.0 }
|
|
|
|
define double @fconst_s64_0() { ret double 0.0 }
|
2017-03-16 00:51:41 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: const_s32
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2017-10-19 07:18:12 +08:00
|
|
|
; CHECK-LABEL: name: const_s32
|
2017-10-25 02:04:54 +08:00
|
|
|
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK: $w0 = COPY [[MOVi32imm]]
|
2017-03-16 00:51:41 +08:00
|
|
|
%0(s32) = G_CONSTANT i32 42
|
2018-02-01 06:04:26 +08:00
|
|
|
$w0 = COPY %0(s32)
|
2017-03-16 00:51:41 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: const_s64
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2017-10-19 07:18:12 +08:00
|
|
|
; CHECK-LABEL: name: const_s64
|
2017-10-25 02:04:54 +08:00
|
|
|
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234567890123
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK: $x0 = COPY [[MOVi64imm]]
|
2017-03-16 00:51:41 +08:00
|
|
|
%0(s64) = G_CONSTANT i64 1234567890123
|
2018-02-01 06:04:26 +08:00
|
|
|
$x0 = COPY %0(s64)
|
2017-03-16 00:51:41 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fconst_s32
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2017-10-19 07:18:12 +08:00
|
|
|
; CHECK-LABEL: name: fconst_s32
|
2017-10-25 02:04:54 +08:00
|
|
|
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1080033280
|
|
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK: $s0 = COPY [[COPY]]
|
2017-03-16 00:51:41 +08:00
|
|
|
%0(s32) = G_FCONSTANT float 3.5
|
2018-02-01 06:04:26 +08:00
|
|
|
$s0 = COPY %0(s32)
|
2017-03-16 00:51:41 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fconst_s64
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2017-10-19 07:18:12 +08:00
|
|
|
; CHECK-LABEL: name: fconst_s64
|
2017-10-25 02:04:54 +08:00
|
|
|
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 4607182418800017408
|
|
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVi64imm]]
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK: $d0 = COPY [[COPY]]
|
2017-03-16 00:51:41 +08:00
|
|
|
%0(s64) = G_FCONSTANT double 1.0
|
2018-02-01 06:04:26 +08:00
|
|
|
$d0 = COPY %0(s64)
|
2017-03-16 00:51:41 +08:00
|
|
|
...
|
[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf.
Summary:
There's only a tablegen testcase for IntImmLeaf and not a CodeGen one
because the relevant rules are rejected for other reasons at the moment.
On AArch64, it's because there's an SDNodeXForm attached to the operand.
On X86, it's because the rule either emits multiple instructions or has
another predicate using PatFrag which cannot easily be supported at the
same time.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36569
llvm-svn: 315761
2017-10-14 05:28:03 +08:00
|
|
|
|
|
|
|
---
|
|
|
|
name: fconst_s32_0
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2017-10-19 07:18:12 +08:00
|
|
|
; CHECK-LABEL: name: fconst_s32_0
|
2017-10-25 02:04:54 +08:00
|
|
|
; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK: $s0 = COPY [[FMOVS0_]]
|
[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf.
Summary:
There's only a tablegen testcase for IntImmLeaf and not a CodeGen one
because the relevant rules are rejected for other reasons at the moment.
On AArch64, it's because there's an SDNodeXForm attached to the operand.
On X86, it's because the rule either emits multiple instructions or has
another predicate using PatFrag which cannot easily be supported at the
same time.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36569
llvm-svn: 315761
2017-10-14 05:28:03 +08:00
|
|
|
%0(s32) = G_FCONSTANT float 0.0
|
2018-02-01 06:04:26 +08:00
|
|
|
$s0 = COPY %0(s32)
|
[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf.
Summary:
There's only a tablegen testcase for IntImmLeaf and not a CodeGen one
because the relevant rules are rejected for other reasons at the moment.
On AArch64, it's because there's an SDNodeXForm attached to the operand.
On X86, it's because the rule either emits multiple instructions or has
another predicate using PatFrag which cannot easily be supported at the
same time.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36569
llvm-svn: 315761
2017-10-14 05:28:03 +08:00
|
|
|
...
|
|
|
|
|
|
|
|
---
|
|
|
|
name: fconst_s64_0
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: fpr }
|
|
|
|
|
|
|
|
body: |
|
|
|
|
bb.0:
|
2017-10-19 07:18:12 +08:00
|
|
|
; CHECK-LABEL: name: fconst_s64_0
|
2017-10-25 02:04:54 +08:00
|
|
|
; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
|
2018-02-01 06:04:26 +08:00
|
|
|
; CHECK: $x0 = COPY [[FMOVD0_]]
|
[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf.
Summary:
There's only a tablegen testcase for IntImmLeaf and not a CodeGen one
because the relevant rules are rejected for other reasons at the moment.
On AArch64, it's because there's an SDNodeXForm attached to the operand.
On X86, it's because the rule either emits multiple instructions or has
another predicate using PatFrag which cannot easily be supported at the
same time.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36569
llvm-svn: 315761
2017-10-14 05:28:03 +08:00
|
|
|
%0(s64) = G_FCONSTANT double 0.0
|
2018-02-01 06:04:26 +08:00
|
|
|
$x0 = COPY %0(s64)
|
[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf.
Summary:
There's only a tablegen testcase for IntImmLeaf and not a CodeGen one
because the relevant rules are rejected for other reasons at the moment.
On AArch64, it's because there's an SDNodeXForm attached to the operand.
On X86, it's because the rule either emits multiple instructions or has
another predicate using PatFrag which cannot easily be supported at the
same time.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: qcolombet
Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36569
llvm-svn: 315761
2017-10-14 05:28:03 +08:00
|
|
|
...
|