2018-09-20 08:26:44 +08:00
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# REQUIRES: ppc
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[ELF][PPC] Allow PT_LOAD to have overlapping p_offset ranges
This change affects the non-linker script case (precisely, when the
`SECTIONS` command is not used). It deletes 3 alignments at PT_LOAD
boundaries for the default case: the size of a powerpc64 binary can be
decreased by at most 192kb. The technique can be ported to other
targets.
Let me demonstrate the idea with a maxPageSize=65536 example:
When assigning the address to the first output section of a new PT_LOAD,
if the end p_vaddr of the previous PT_LOAD is 0x10020, we advance to
the next multiple of maxPageSize: 0x20000. The new PT_LOAD will thus
have p_vaddr=0x20000. Because p_offset and p_vaddr are congruent modulo
maxPageSize, p_offset will be 0x20000, leaving a p_offset gap [0x10020,
0x20000) in the output.
Alternatively, if we advance to 0x20020, the new PT_LOAD will have
p_vaddr=0x20020. We can pick either 0x10020 or 0x20020 for p_offset!
Obviously 0x10020 is the choice because it leaves no gap. At runtime,
p_vaddr will be rounded down by pagesize (65536 if
pagesize=maxPageSize). This PT_LOAD will load additional initial
contents from p_offset ranges [0x10000,0x10020), which will also be
loaded by the previous PT_LOAD. This is fine if -z noseparate-code is in
effect or if we are not transiting between executable and non-executable
segments.
ld.bfd -z noseparate-code leverages this technique to keep output small.
This patch implements the technique in lld, which is mostly effective on
targets with large defaultMaxPageSize (AArch64/MIPS/PPC: 65536). The 3
removed alignments can save almost 3*65536 bytes.
Two places that rely on p_vaddr%pagesize = 0 have to be updated.
1) We used to round p_memsz(PT_GNU_RELRO) up to commonPageSize (defaults
to 4096 on all targets). Now p_vaddr%commonPageSize may be non-zero.
The updated formula takes account of that factor.
2) Our TP offsets formulae are only correct if p_vaddr%p_align = 0.
Fix them. See the updated comments in InputSection.cpp for details.
On targets that we enable the technique (only PPC64 now),
we can potentially make `p_vaddr(PT_TLS)%p_align(PT_TLS) != 0`
if `sh_addralign(.tdata) < sh_addralign(.tbss)`
This exposes many problems in ld.so implementations, especially the
offsets of dynamic TLS blocks. Known issues:
FreeBSD 13.0-CURRENT rtld-elf (i386/amd64/powerpc/arm64)
glibc (HEAD) i386 and x86_64 https://sourceware.org/bugzilla/show_bug.cgi?id=24606
musl<=1.1.22 on TLS Variant I architectures (aarch64/powerpc64/...)
So, force p_vaddr%p_align = 0 by rounding dot up to p_align(PT_TLS).
The technique will be enabled (with updated tests) for other targets in
subsequent patches.
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D64906
llvm-svn: 369343
2019-08-20 16:34:25 +08:00
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# XFAIL: *
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2018-09-20 08:26:44 +08:00
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# RUN: llvm-readelf -relocations --wide %p/Inputs/ppc64le-quadword-ldst.o | FileCheck --check-prefix=QuadInputRelocs %s
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# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %p/Inputs/shared-ppc64.s -o %t2.o
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# RUN: ld.lld -shared %t2.o -o %t2.so
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# RUN: ld.lld %t2.so %p/Inputs/ppc64le-quadword-ldst.o -o %t
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2019-04-23 19:47:28 +08:00
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# RUN: llvm-objdump -d %t | FileCheck --check-prefix=Dis %s
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2018-09-20 08:26:44 +08:00
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# RUN: ld.lld --no-toc-optimize %t2.so %p/Inputs/ppc64le-quadword-ldst.o -o %t
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2019-04-23 19:47:28 +08:00
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# RUN: llvm-objdump -d %t | FileCheck --check-prefix=NoOpt %s
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2018-09-20 08:26:44 +08:00
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# QuadInputRelocs: Relocation section '.rela.text'
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# QuadInputRelocs: R_PPC64_TOC16_LO_DS 0000000000000000 quadLd
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# QuadInputRelocs: R_PPC64_TOC16_LO_DS 0000000000000010 quadSt
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# The powerpc backend doesn't support the quadword load/store instructions yet.
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# So they are tested by linking against an object file assembled with
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# `as -mpower9 -o ppc64le-quadword-ldst.o in.s` and checking the encoding of
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# the unknown instructions in the dissasembly. Source used as input:
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#quads:
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#.Lbegin_quads:
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#.Lgep_quads:
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# addis 2, 12, .TOC.-.Lgep_quads@ha
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# addi 2, 2, .TOC.-.Lgep_quads@l
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#.Llep_quads:
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#.localentry quads, .Llep_quads-.Lgep_quads
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# addis 3, 2, quadLd@toc@ha
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# lq 4, quadLd@toc@l(3)
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# addis 3, 2, quadSt@toc@ha
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# stq 4, quadSt@toc@l(3)
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# blr
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#
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# .p2align 4
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# .global quadLd
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# .lcomm quadLd, 16
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#
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# .global quadSt
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# .lcomm quadSt, 16
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# e0 82 7f 70 decodes to | 111000 | 00100 | 00010 | 16-bit imm |
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# | 56 | 4 | 2 | 32624 |
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# which is `lq r4, 32624(r2)`
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# f8 82 7f 82 decodes to | 111110 | 00100 | 00010 | 14-bit imm | 10 |
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# | 62 | 4 | 2 | 8160 | 2 |
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# The immediate represents a word offset so this dissasembles to:
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# `stq r4, 32640(r2)`
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# Dis-LABEL: quads:
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# Dis-NEXT: addis
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# Dis-NEXT: addi
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# Dis-NEXT: nop
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# Dis-NEXT: 70 7f 82 e0 <unknown>
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# Dis-NEXT: nop
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# Dis-NEXT: 82 7f 82 f8 <unknown>
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# Dis-NEXT: blr
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# e0 83 7f 70 decodes to | 111000 | 00100 | 00011 | 16-bit imm |
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# | 56 | 4 | 3 | 32624 |
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# `lq r4, 32624(r3)`
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# f8 83 7f 82 decodes to | 111110 | 00100 | 00010 | 14-bit imm | 10 |
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# | 62 | 4 | 2 | 8160 | 2 |
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# `stq r4, 32640(r3)`
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# NoOpt-LABEL: quads:
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# NoOpt-NEXT: addis
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# NoOpt-NEXT: addi
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# NoOpt-NEXT: addis 3, 2, 0
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# NoOpt-NEXT: 70 7f 83 e0 <unknown>
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# NoOpt-NEXT: addis 3, 2, 0
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# NoOpt-NEXT: 82 7f 83 f8 <unknown>
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# NoOpt-NEXT: blr
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