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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir

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AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s 2> %t | FileCheck -check-prefix=GCN %s
# RUN: FileCheck -check-prefix=ERR %s < %t
# ERR-NOT: remark:
# ERR: remark: <unknown>:0:0: cannot select: %1:sgpr(s64), %2:sgpr(s64), %3:sgpr(s64) = G_UNMERGE_VALUES %0:sgpr(s192) (in function: test_unmerge_values_s_s64_s_s64_s64_s_s192)
# ERR-NOT: remark:
---
name: test_unmerge_values_v_s32_v_s32_v_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GCN-LABEL: name: test_unmerge_values_v_s32_v_s32_v_s64
; GCN: liveins: $vgpr0_vgpr1
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2
...
---
name: test_unmerge_values_s_s32_s_s32_s_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s_s64
; GCN: liveins: $sgpr0_sgpr1
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2
...
---
name: test_unmerge_values_v_s32_s_s32_s_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; GCN-LABEL: name: test_unmerge_values_v_s32_s_s32_s_s64
; GCN: liveins: $sgpr0_sgpr1
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2
...
---
name: test_unmerge_values_s_s32_v_s32_s_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64
; GCN: liveins: $sgpr0_sgpr1
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2
...
---
name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY undef %2.sub0:sreg_64
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY undef %2.sub1:sreg_64
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]]
%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES undef %0:sgpr(s64)
S_ENDPGM 0, implicit %1, implicit %2
...
---
name: test_unmerge_values_s_s32_s_s32_s32_s_s96
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2
; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s96
; GCN: liveins: $sgpr0_sgpr1_sgpr2
; GCN: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub2
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]]
%0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
%1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2, implicit %3
...
---
name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
2019-10-10 15:11:33 +08:00
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub2
; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub3
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]]
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32), %4:sgpr(s32) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2, implicit %3, implicit %4
...
---
name: test_unmerge_values_s_s64_s_s64_s_s128
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-LABEL: name: test_unmerge_values_s_s64_s_s64_s_s128
; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
2019-10-10 15:11:33 +08:00
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[COPY]].sub0_sub1
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[COPY]].sub2_sub3
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:sgpr(s64), %2:sgpr(s64) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2
...
---
name: test_unmerge_values_s_s64_s_s64_s64_s_s192
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3
AMDGPU/GlobalISel: Increase max legal size to 1024 There are 1024 bit register classes defined for AGPRs. Additionally OpenCL defines vectors up to 16 x i64, and this helps those tests legalize. llvm-svn: 373350
2019-10-02 00:35:06 +08:00
; GCN-LABEL: name: test_unmerge_values_s_s64_s_s64_s64_s_s192
; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GCN: [[DEF:%[0-9]+]]:sgpr(s192) = G_IMPLICIT_DEF
; GCN: [[UV:%[0-9]+]]:sgpr(s64), [[UV1:%[0-9]+]]:sgpr(s64), [[UV2:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[DEF]](s192)
; GCN: S_ENDPGM 0, implicit [[UV]](s64), implicit [[UV1]](s64), implicit [[UV2]](s64)
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES llvm-svn: 365483
2019-07-09 22:02:26 +08:00
%0:sgpr(s192) = G_IMPLICIT_DEF
%1:sgpr(s64), %2:sgpr(s64), %3:sgpr(s64) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2, implicit %3
...
---
name: test_unmerge_values_rc_set_def_v_s32_v_s32_v_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GCN-LABEL: name: test_unmerge_values_rc_set_def_v_s32_v_s32_v_s64
; GCN: liveins: $vgpr0_vgpr1
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr_32(s32), %2:vgpr_32(s32) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2
...
---
name: test_unmerge_values_rc_set_use_v_s32_v_s32_v_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GCN-LABEL: name: test_unmerge_values_rc_set_use_v_s32_v_s32_v_s64
; GCN: liveins: $vgpr0_vgpr1
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
%0:vreg_64(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2
...
AMDGPU/GlobalISel: Increase max legal size to 1024 There are 1024 bit register classes defined for AGPRs. Additionally OpenCL defines vectors up to 16 x i64, and this helps those tests legalize. llvm-svn: 373350
2019-10-02 00:35:06 +08:00
---
name: test_unmerge_values_s_s256_s_s1024
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GCN-LABEL: name: test_unmerge_values_s_s256_s_s1024
; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
; GCN: [[DEF:%[0-9]+]]:sreg_1024 = IMPLICIT_DEF
; GCN: [[COPY:%[0-9]+]]:sreg_256 = COPY [[DEF]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
; GCN: [[COPY1:%[0-9]+]]:sreg_256 = COPY [[DEF]].sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
; GCN: [[COPY2:%[0-9]+]]:sreg_256 = COPY [[DEF]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23
; GCN: [[COPY3:%[0-9]+]]:sreg_256 = COPY [[DEF]].sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]]
%0:sgpr(s1024) = G_IMPLICIT_DEF
%1:sgpr(s256), %2:sgpr(s256), %3:sgpr(s256), %4:sgpr(s256) = G_UNMERGE_VALUES %0
S_ENDPGM 0, implicit %1, implicit %2, implicit %3, implicit %4
...