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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir

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AMDGPU/GlobalISel: Select G_PTRTOINT llvm-svn: 373715
2019-10-04 16:35:37 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: ptrtoint_s_p3_to_s_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptrtoint_s_p3_to_s_s32
; CHECK: liveins: $sgpr0
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
AMDGPU/GlobalISel: Select G_PTRTOINT llvm-svn: 373715
2019-10-04 16:35:37 +08:00
; CHECK: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(p3) = COPY $sgpr0
%1:sgpr(s32) = G_PTRTOINT %0
S_ENDPGM 0, implicit %1
...
---
name: ptrtoint_s_p5_to_s_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptrtoint_s_p5_to_s_s32
; CHECK: liveins: $sgpr0
AMDGPU: Relax 32-bit SGPR register class Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This will allow the register coalescer to do a better job eliminating copies to m0. For GlobalISel, as a terrible hack, use SGPR_32 for things that should use SCC until booleans are solved. llvm-svn: 375267
2019-10-19 02:26:37 +08:00
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
AMDGPU/GlobalISel: Select G_PTRTOINT llvm-svn: 373715
2019-10-04 16:35:37 +08:00
; CHECK: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(p5) = COPY $sgpr0
%1:sgpr(s32) = G_PTRTOINT %0
S_ENDPGM 0, implicit %1
...
---
name: ptrtoint_s_p0_to_s_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrtoint_s_p0_to_s_s64
; CHECK: liveins: $sgpr0_sgpr1
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Select G_PTRTOINT llvm-svn: 373715
2019-10-04 16:35:37 +08:00
; CHECK: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_PTRTOINT %0
S_ENDPGM 0, implicit %1
...
---
name: ptrtoint_s_p1_to_s_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrtoint_s_p1_to_s_s64
; CHECK: liveins: $sgpr0_sgpr1
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Select G_PTRTOINT llvm-svn: 373715
2019-10-04 16:35:37 +08:00
; CHECK: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(p1) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_PTRTOINT %0
S_ENDPGM 0, implicit %1
...
---
name: ptrtoint_s_p999_to_s_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrtoint_s_p999_to_s_s64
; CHECK: liveins: $sgpr0_sgpr1
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
2020-01-13 06:10:18 +08:00
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Select G_PTRTOINT llvm-svn: 373715
2019-10-04 16:35:37 +08:00
; CHECK: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(p999) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_PTRTOINT %0
S_ENDPGM 0, implicit %1
...