2019-07-16 03:50:07 +08:00
|
|
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
2019-09-30 14:31:30 +08:00
|
|
|
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
|
|
|
|
|
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
|
2019-07-16 03:50:07 +08:00
|
|
|
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
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|
|
|
|
|
---
|
|
|
|
|
|
2019-07-16 03:50:07 +08:00
|
|
|
name: or_s1_vcc_vcc_vcc
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
2019-07-16 03:50:07 +08:00
|
|
|
tracksRegLiveness: true
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
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|
|
body: |
|
|
|
|
|
bb.0:
|
2019-07-16 03:50:07 +08:00
|
|
|
liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_s1_vcc_vcc_vcc
|
|
|
|
|
; WAVE64: liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
|
|
|
; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
|
|
|
|
; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
|
|
|
|
|
; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
|
|
|
|
|
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc
|
|
|
|
|
; WAVE32: liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
|
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
|
|
|
; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
|
|
|
|
|
; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
|
|
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
|
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
|
|
|
%2:vgpr(s32) = G_CONSTANT i32 0
|
|
|
|
|
%3:vcc(s1) = G_ICMP intpred(eq), %0, %2
|
|
|
|
|
%4:vcc(s1) = G_ICMP intpred(eq), %1, %2
|
|
|
|
|
%5:vcc(s1) = G_OR %3, %4
|
|
|
|
|
S_ENDPGM 0, implicit %5
|
|
|
|
|
...
|
|
|
|
|
|
AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-03 00:30:59 +08:00
|
|
|
# Should fail to select
|
2019-07-16 03:50:07 +08:00
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s1_sgpr_sgpr_sgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $sgpr0, $sgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_s1_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE64: liveins: $sgpr0, $sgpr1
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_s1_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE32: liveins: $sgpr0, $sgpr1
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
|
|
|
%1:sgpr(s32) = COPY $sgpr1
|
2019-07-16 03:50:07 +08:00
|
|
|
%2:sgpr(s1) = G_TRUNC %0
|
|
|
|
|
%3:sgpr(s1) = G_TRUNC %1
|
|
|
|
|
%4:sgpr(s1) = G_OR %2, %3
|
|
|
|
|
S_ENDPGM 0, implicit %4
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s16_sgpr_sgpr_sgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $sgpr0, $sgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_s16_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE64: liveins: $sgpr0, $sgpr1
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 22:28:30 +08:00
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32-LABEL: name: or_s16_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE32: liveins: $sgpr0, $sgpr1
|
2019-07-16 22:28:30 +08:00
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 22:28:30 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
2019-07-16 03:50:07 +08:00
|
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
|
|
|
%1:sgpr(s32) = COPY $sgpr1
|
|
|
|
|
%2:sgpr(s16) = G_TRUNC %0
|
|
|
|
|
%3:sgpr(s16) = G_TRUNC %1
|
|
|
|
|
%4:sgpr(s16) = G_OR %2, %3
|
|
|
|
|
S_ENDPGM 0, implicit %4
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s16_vgpr_vgpr_vgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_s16_vgpr_vgpr_vgpr
|
|
|
|
|
; WAVE64: liveins: $vgpr0, $vgpr1
|
2019-09-30 14:31:30 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
|
|
|
; WAVE64: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32-LABEL: name: or_s16_vgpr_vgpr_vgpr
|
|
|
|
|
; WAVE32: liveins: $vgpr0, $vgpr1
|
2019-09-13 11:55:43 +08:00
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
|
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
|
|
|
; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
|
2019-07-16 03:50:07 +08:00
|
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
|
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
|
|
|
%2:vgpr(s16) = G_TRUNC %0
|
|
|
|
|
%3:vgpr(s16) = G_TRUNC %1
|
|
|
|
|
%4:vgpr(s16) = G_OR %2, %3
|
|
|
|
|
S_ENDPGM 0, implicit %4
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s32_sgpr_sgpr_sgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $sgpr0, $sgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_s32_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE64: liveins: $sgpr0, $sgpr1
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_s32_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE32: liveins: $sgpr0, $sgpr1
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
|
|
|
%1:sgpr(s32) = COPY $sgpr1
|
|
|
|
|
%2:sgpr(s32) = G_OR %0, %1
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s64_sgpr_sgpr_sgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
|
|
|
|
; WAVE64-LABEL: name: or_s64_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_s64_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
|
|
|
|
%1:sgpr(s64) = COPY $sgpr2_sgpr3
|
|
|
|
|
%2:sgpr(s64) = G_OR %0, %1
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_v2s16_sgpr_sgpr_sgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $sgpr0, $sgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE64: liveins: $sgpr0, $sgpr1
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE32: liveins: $sgpr0, $sgpr1
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
%0:sgpr(<2 x s16>) = COPY $sgpr0
|
|
|
|
|
%1:sgpr(<2 x s16>) = COPY $sgpr1
|
|
|
|
|
%2:sgpr(<2 x s16>) = G_OR %0, %1
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_v2s32_sgpr_sgpr_sgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
|
|
|
|
; WAVE64-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
%0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
|
|
|
|
|
%1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
|
|
|
|
|
%2:sgpr(<2 x s32>) = G_OR %0, %1
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
|
2019-07-16 03:50:07 +08:00
|
|
|
name: or_v4s16_sgpr_sgpr_sgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
|
2019-07-16 03:50:07 +08:00
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
|
|
|
|
; WAVE64-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
|
|
|
|
|
; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
|
|
|
|
|
%1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
|
|
|
|
%2:sgpr(<4 x s16>) = G_OR %0, %1
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
|
2019-07-16 03:50:07 +08:00
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s32_vgpr_vgpr_vgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_s32_vgpr_vgpr_vgpr
|
|
|
|
|
; WAVE64: liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
|
|
|
; WAVE64: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY]], [[COPY1]], implicit $exec
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e32_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_s32_vgpr_vgpr_vgpr
|
|
|
|
|
; WAVE32: liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
|
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
2020-01-23 10:36:26 +08:00
|
|
|
; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
|
2019-07-16 03:50:07 +08:00
|
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
|
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
|
|
|
%2:vgpr(s32) = G_OR %0, %1
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_v2s16_vgpr_vgpr_vgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
|
|
|
|
|
; WAVE64: liveins: $vgpr0, $vgpr1
|
2019-09-30 14:31:30 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
|
|
|
; WAVE64: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
|
|
|
|
|
; WAVE32: liveins: $vgpr0, $vgpr1
|
2019-09-30 14:31:30 +08:00
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
|
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
|
|
|
; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
|
|
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
|
2019-07-16 03:50:07 +08:00
|
|
|
%0:vgpr(<2 x s16>) = COPY $vgpr0
|
|
|
|
|
%1:vgpr(<2 x s16>) = COPY $vgpr1
|
|
|
|
|
%2:vgpr(<2 x s16>) = G_OR %0, %1
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
# This should fail to select
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s64_vgpr_vgpr_vgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
|
|
|
|
; WAVE64-LABEL: name: or_s64_vgpr_vgpr_vgpr
|
|
|
|
|
; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
|
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
|
|
|
|
; WAVE64: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[OR]](s64)
|
|
|
|
|
; WAVE32-LABEL: name: or_s64_vgpr_vgpr_vgpr
|
|
|
|
|
; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
|
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
|
|
|
|
; WAVE32: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
|
|
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[OR]](s64)
|
|
|
|
|
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
|
|
|
|
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
|
|
|
|
%2:vgpr(s64) = G_OR %0, %1
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s1_vcc_undef_vcc_undef_vcc
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
; WAVE64-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
|
|
|
|
|
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 undef %1:sreg_64, undef %2:sreg_64
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
%2:vcc(s1) = G_OR undef %0:vcc(s1), undef %1:vcc(s1)
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
|
2019-07-16 03:50:07 +08:00
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s1_sgpr_undef_sgpr_undef_sgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
; WAVE64-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
2019-12-20 19:08:36 +08:00
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32, implicit-def dead $scc
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
%2:sgpr(s1) = G_OR undef %0:sgpr(s1), undef %1:sgpr(s1)
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s1_vgpr_undef_vgpr_undef_vgpr
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
; WAVE64-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
|
|
|
|
|
; WAVE64: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
|
|
|
|
|
; WAVE32-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
|
|
|
|
|
; WAVE32: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
|
|
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
|
|
|
|
|
%2:vgpr(s1) = G_OR undef %0:vgpr(s1), undef %1:vgpr(s1)
|
|
|
|
|
S_ENDPGM 0, implicit %2
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
name: or_s1_vcc_copy_to_vcc
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE64-LABEL: name: or_s1_vcc_copy_to_vcc
|
|
|
|
|
; WAVE64: liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-03 00:30:59 +08:00
|
|
|
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
|
|
|
|
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
|
|
|
|
; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
|
|
|
|
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
|
|
|
|
; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc
|
|
|
|
|
; WAVE32: liveins: $vgpr0, $vgpr1
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
|
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-03 00:30:59 +08:00
|
|
|
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
|
|
|
|
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
|
|
|
|
; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
|
|
|
|
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
|
|
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
|
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
|
|
|
%2:vgpr(s1) = G_TRUNC %0
|
|
|
|
|
%3:vgpr(s1) = G_TRUNC %1
|
|
|
|
|
%4:vcc(s1) = COPY %2
|
|
|
|
|
%5:vcc(s1) = COPY %3
|
|
|
|
|
%6:vcc(s1) = G_OR %4, %5
|
|
|
|
|
S_ENDPGM 0, implicit %6
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
# The selector for the copy of the or result may constrain the result
|
|
|
|
|
# register of the or, losing that it is a VCCRegBank context.
|
|
|
|
|
|
|
|
|
|
# Works for wave32, should fail for wave64
|
|
|
|
|
---
|
|
|
|
|
name: copy_select_constrain_vcc_result_reg_wave32
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $vgpr0
|
|
|
|
|
|
|
|
|
|
; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
|
|
|
|
|
; WAVE64: liveins: $vgpr0
|
2019-08-28 10:11:03 +08:00
|
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-03 00:30:59 +08:00
|
|
|
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
|
|
|
|
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
|
|
|
|
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
|
|
|
|
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
|
|
|
|
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
|
|
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B64_]]
|
|
|
|
|
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
2019-07-16 03:50:07 +08:00
|
|
|
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
|
|
|
|
|
; WAVE32: liveins: $vgpr0
|
|
|
|
|
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
|
|
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-03 00:30:59 +08:00
|
|
|
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
|
|
|
|
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
|
|
|
|
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
|
|
|
|
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
2019-10-19 02:26:37 +08:00
|
|
|
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
|
|
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
|
|
|
|
|
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
2019-07-16 03:50:07 +08:00
|
|
|
%1:vgpr(s32) = COPY $vgpr0
|
|
|
|
|
%0:vgpr(s1) = G_TRUNC %1(s32)
|
|
|
|
|
%2:sgpr(s1) = G_CONSTANT i1 true
|
|
|
|
|
%6:sgpr(s32) = G_CONSTANT i32 0
|
|
|
|
|
%7:sgpr(p1) = G_IMPLICIT_DEF
|
|
|
|
|
%9:vcc(s1) = COPY %0(s1)
|
|
|
|
|
%10:vcc(s1) = COPY %2(s1)
|
|
|
|
|
%8:vcc(s1) = G_OR %9, %10
|
|
|
|
|
%3:sreg_32_xm0(s1) = COPY %8(s1)
|
|
|
|
|
S_ENDPGM 0, implicit %3
|
|
|
|
|
|
|
|
|
|
...
|
|
|
|
|
|
|
|
|
|
# Works for wave64, should fail for wave32
|
|
|
|
|
---
|
|
|
|
|
name: copy_select_constrain_vcc_result_reg_wave64
|
|
|
|
|
legalized: true
|
|
|
|
|
regBankSelected: true
|
|
|
|
|
tracksRegLiveness: true
|
|
|
|
|
body: |
|
|
|
|
|
bb.0:
|
|
|
|
|
liveins: $vgpr0
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
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2019-07-16 03:50:07 +08:00
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; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
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; WAVE64: liveins: $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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2019-10-19 02:26:37 +08:00
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; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
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AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-03 00:30:59 +08:00
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; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
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; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
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; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
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; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
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2019-07-16 03:50:07 +08:00
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; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B64_]]
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; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
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; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
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; WAVE32: liveins: $vgpr0
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2019-08-28 10:11:03 +08:00
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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2019-10-19 02:26:37 +08:00
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; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
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AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns,
which would fail due to inferring the SGPR reg bank for virtual
registers with a set register class instead of VCC bank. Use
instruction selection would constrain the virtual register to a
specific class, so when the def was selected later the bank no longer
was set to VCC.
Remove the SCC reg bank. SCC isn't directly addressable, so it
requires copying from SCC to an allocatable 32-bit register during
selection, so these might as well be treated as 32-bit SGPR values.
Now any scalar boolean value that will produce an outupt in SCC should
be widened during RegBankSelect to s32. Any s1 value should be a
vector boolean during selection. This makes the vcc register bank
unambiguous with a normal SGPR during selection.
Summary of how this should now work:
- G_TRUNC is always a no-op, and never should use a vcc bank result.
- SALU boolean operations should be promoted to s32 in RegBankSelect
apply mapping
- An s1 value means vcc bank at selection. The exception is for
legalization artifacts that use s1, which are never VCC. All other
contexts should infer the VCC register classes for s1 typed
registers. The LLT for the register is now needed to infer the
correct register class. Extensions with vcc sources should be
legalized to a select of constants during RegBankSelect.
- Copy from non-vcc to vcc ensures high bits of the input value are
cleared during selection.
- SALU boolean inputs should ensure the inputs are 0/1. This includes
select, conditional branches, and carry-ins.
There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT
selection ignores the usual register-bank from register class
functions, and can't handle truncates with VCC result banks. I think
this is OK, since the artifacts are specially treated anyway. This
does require some care to avoid producing cases with vcc. There will
also be no 100% reliable way to verify this rule is followed in
selection in case of register classes, and violations manifests
themselves as invalid copy instructions much later.
Standard phi handling also only considers the bank of the result
register, and doesn't insert copies to make the source banks
match. This doesn't work for vcc, so we have to manually correct phi
inputs in this case. We should add a verifier check to make sure there
are no phis with mixed vcc and non-vcc register bank inputs.
There's also some duplication with the LegalizerHelper, and some code
which should live in the helper. I don't see a good way to share
special knowledge about what types to use for intermediate operations
depending on the bank for example. Using the helper to replace
extensions with selects also seems somewhat awkward to me.
Another issue is there are some contexts calling
getRegBankFromRegClass that apparently don't have the LLT type for the
register, but I haven't yet run into a real issue from this.
This also introduces new unnecessary instructions in most cases, since
we don't yet try to optimize out the zext when the source is known to
come from a compare.
2019-11-03 00:30:59 +08:00
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; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
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; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
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; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
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; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
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; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
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2019-10-19 02:26:37 +08:00
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
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; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
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2019-07-16 03:50:07 +08:00
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%1:vgpr(s32) = COPY $vgpr0
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%0:vgpr(s1) = G_TRUNC %1(s32)
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%2:sgpr(s1) = G_CONSTANT i1 true
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%6:sgpr(s32) = G_CONSTANT i32 0
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%7:sgpr(p1) = G_IMPLICIT_DEF
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%9:vcc(s1) = COPY %0(s1)
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%10:vcc(s1) = COPY %2(s1)
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%8:vcc(s1) = G_OR %9, %10
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%3:sreg_64_xexec(s1) = COPY %8(s1)
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S_ENDPGM 0, implicit %3
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AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
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...
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