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llvm-project/llvm/test/CodeGen/PTX/sub.ll

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PTX: Add intrinsics to list of built-in intrinsics, which allows them to be used by Clang. To help Clang integration, the PTX target has been split into two targets: ptx32 and ptx64, depending on the desired pointer size. - Add GCCBuiltin class to all intrinsics - Split PTX target into ptx32 and ptx64 llvm-svn: 129851
2011-04-20 23:37:17 +08:00
; RUN: llc < %s -march=ptx32 | FileCheck %s
Add simple arithmetics and %type directive for PTX llvm-svn: 119485
2010-11-17 16:08:49 +08:00
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
define ptx_device i16 @t1_u16(i16 %x, i16 %y) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: sub.u16 rh{{[0-9]+}}, rh{{[0-9]+}}, rh{{[0-9]+}};
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
; CHECK-NEXT: ret;
%z = sub i16 %x, %y
ret i16 %z
}
define ptx_device i32 @t1_u32(i32 %x, i32 %y) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: sub.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}};
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
; CHECK-NEXT: ret;
Add simple arithmetics and %type directive for PTX llvm-svn: 119485
2010-11-17 16:08:49 +08:00
%z = sub i32 %x, %y
ret i32 %z
}
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
define ptx_device i64 @t1_u64(i64 %x, i64 %y) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: sub.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}};
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
; CHECK-NEXT: ret;
%z = sub i64 %x, %y
ret i64 %z
Add simple arithmetics and %type directive for PTX llvm-svn: 119485
2010-11-17 16:08:49 +08:00
}
Add preliminary support for .f32 in the PTX backend. - Add appropriate TableGen patterns for fadd, fsub, fmul. - Add .f32 as the PTX type for the LLVM float type. - Allow parameters, return values, and global variable declarations to accept the float type. - Add appropriate test cases. Patch by Justin Holewinski llvm-svn: 126636
2011-02-28 14:34:09 +08:00
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
define ptx_device float @t1_f32(float %x, float %y) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: sub.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
Add preliminary support for .f32 in the PTX backend. - Add appropriate TableGen patterns for fadd, fsub, fmul. - Add .f32 as the PTX type for the LLVM float type. - Allow parameters, return values, and global variable declarations to accept the float type. - Add appropriate test cases. Patch by Justin Holewinski llvm-svn: 126636
2011-02-28 14:34:09 +08:00
; CHECK-NEXT: ret;
%z = fsub float %x, %y
ret float %z
}
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
define ptx_device double @t1_f64(double %x, double %y) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: sub.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
; CHECK-NEXT: ret;
%z = fsub double %x, %y
ret double %z
}
define ptx_device i16 @t2_u16(i16 %x) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: add.u16 rh{{[0-9]+}}, rh{{[0-9]+}}, -1;
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
; CHECK-NEXT: ret;
%z = sub i16 %x, 1
ret i16 %z
}
define ptx_device i32 @t2_u32(i32 %x) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: add.u32 r{{[0-9]+}}, r{{[0-9]+}}, -1;
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
; CHECK-NEXT: ret;
%z = sub i32 %x, 1
ret i32 %z
}
define ptx_device i64 @t2_u64(i64 %x) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: add.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, -1;
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
; CHECK-NEXT: ret;
%z = sub i64 %x, 1
ret i64 %z
}
define ptx_device float @t2_f32(float %x) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: add.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, 0FBF800000;
Add preliminary support for .f32 in the PTX backend. - Add appropriate TableGen patterns for fadd, fsub, fmul. - Add .f32 as the PTX type for the LLVM float type. - Allow parameters, return values, and global variable declarations to accept the float type. - Add appropriate test cases. Patch by Justin Holewinski llvm-svn: 126636
2011-02-28 14:34:09 +08:00
; CHECK-NEXT: ret;
%z = fsub float %x, 1.0
ret float %z
}
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
define ptx_device double @t2_f64(double %x) {
PTX: Always use registers for return values, but use .param space for device parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
2011-06-24 02:10:13 +08:00
; CHECK: add.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, 0DBFF0000000000000;
Extend initial support for primitive types in PTX backend - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
2011-03-02 11:20:28 +08:00
; CHECK-NEXT: ret;
%z = fsub double %x, 1.0
ret double %z
}