forked from OSchip/llvm-project
38 lines
1.4 KiB
LLVM
38 lines
1.4 KiB
LLVM
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-gnu"
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; This test verifies that we can enable subtarget features via
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; the function attributes and generate appropriate code (or,
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; in this case, select the instruction at all).
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; Function Attrs: nounwind
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define <16 x i8> @foo(<16 x i8> %data, <16 x i8> %key) #0 {
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entry:
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%__p0.addr.i = alloca <16 x i8>, align 16
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%__p1.addr.i = alloca <16 x i8>, align 16
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%__ret.i = alloca <16 x i8>, align 16
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%data.addr = alloca <16 x i8>, align 16
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%key.addr = alloca <16 x i8>, align 16
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store <16 x i8> %data, <16 x i8>* %data.addr, align 16
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store <16 x i8> %key, <16 x i8>* %key.addr, align 16
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%0 = load <16 x i8>, <16 x i8>* %data.addr, align 16
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%1 = load <16 x i8>, <16 x i8>* %key.addr, align 16
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store <16 x i8> %0, <16 x i8>* %__p0.addr.i, align 16
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store <16 x i8> %1, <16 x i8>* %__p1.addr.i, align 16
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%2 = load <16 x i8>, <16 x i8>* %__p0.addr.i, align 16
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%3 = load <16 x i8>, <16 x i8>* %__p1.addr.i, align 16
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%vaeseq_v.i = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %2, <16 x i8> %3)
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store <16 x i8> %vaeseq_v.i, <16 x i8>* %__ret.i, align 16
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%4 = load <16 x i8>, <16 x i8>* %__ret.i, align 16
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ret <16 x i8> %4
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}
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; CHECK: foo
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; CHECK: aese
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>)
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attributes #0 = { nounwind "target-features"="+neon,+crc,+crypto" }
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