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llvm-project/clang/test/CodeGen/arm-vector-align.c

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Tests: check for target availability for target-specific tests. Lots of tests are using an explicit target triple w/o first checking that the target is actually available. Add a REQUIRES clause to a bunch of them. This should hopefully unbreak bots which don't configure w/ all targets enabled. llvm-svn: 159949
2012-07-10 02:34:21 +08:00
// REQUIRES: arm-registered-target
Add a testcase for svn r129964 (Neon load/store intrinsic alignments). llvm-svn: 129979
2011-04-22 12:06:49 +08:00
// RUN: %clang_cc1 -triple thumbv7-apple-darwin \
// RUN: -target-abi apcs-gnu \
// RUN: -target-cpu cortex-a8 \
// RUN: -mfloat-abi soft \
// RUN: -target-feature +soft-float-abi \
// RUN: -ffreestanding \
// RUN: -emit-llvm -w -o - %s | FileCheck %s
#include <arm_neon.h>
// Radar 9311427: Check that alignment specifier is used in Neon load/store
// intrinsics.
typedef float AlignedAddr __attribute__ ((aligned (16)));
void t1(AlignedAddr *addr1, AlignedAddr *addr2) {
Preserve alignment for Neon vld1_lane/dup and vst1_lane intrinsics. We had been generating load/store instructions with the default alignment for the vector element type, even when the pointer argument had less alignment. <rdar://problem/10538555> llvm-svn: 149794
2012-02-05 07:58:08 +08:00
// CHECK: @t1
Add a testcase for svn r129964 (Neon load/store intrinsic alignments). llvm-svn: 129979
2011-04-22 12:06:49 +08:00
// CHECK: call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %{{.*}}, i32 16)
float32x4_t a = vld1q_f32(addr1);
// CHECK: call void @llvm.arm.neon.vst1.v4f32(i8* %{{.*}}, <4 x float> %{{.*}}, i32 16)
vst1q_f32(addr2, a);
}
Preserve alignment for Neon vld1_lane/dup and vst1_lane intrinsics. We had been generating load/store instructions with the default alignment for the vector element type, even when the pointer argument had less alignment. <rdar://problem/10538555> llvm-svn: 149794
2012-02-05 07:58:08 +08:00
// Radar 10538555: Make sure unaligned load/stores do not gain alignment.
void t2(char *addr) {
// CHECK: @t2
// CHECK: load i32* %{{.*}}, align 1
int32x2_t vec = vld1_dup_s32(addr);
// CHECK: store i32 %{{.*}}, i32* {{.*}}, align 1
vst1_lane_s32(addr, vec, 1);
}