2018-12-06 22:33:40 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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2019-05-10 08:09:01 +08:00
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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2018-12-06 22:33:40 +08:00
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; ===================================================================================
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; V_LSHL_OR_B32
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; ===================================================================================
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define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: shl_or:
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; VI: ; %bb.0:
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; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
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; VI-NEXT: v_or_b32_e32 v0, v0, v2
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: shl_or:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, v2
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; GFX9-NEXT: ; return to shader part epilog
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2019-05-10 08:09:01 +08:00
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;
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; GFX10-LABEL: shl_or:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, v2
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2019-06-20 23:08:34 +08:00
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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2019-05-10 08:09:01 +08:00
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; GFX10-NEXT: ; return to shader part epilog
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2018-12-06 22:33:40 +08:00
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%x = shl i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
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; VI-LABEL: shl_or_vgpr_c:
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; VI: ; %bb.0:
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; VI-NEXT: s_lshl_b32 s0, s2, s3
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; VI-NEXT: v_or_b32_e32 v0, s0, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: shl_or_vgpr_c:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_lshl_b32 s0, s2, s3
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; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
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; GFX9-NEXT: ; return to shader part epilog
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2019-05-10 08:09:01 +08:00
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;
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; GFX10-LABEL: shl_or_vgpr_c:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_or_b32 v0, s2, s3, v0
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2019-06-20 23:08:34 +08:00
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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2019-05-10 08:09:01 +08:00
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; GFX10-NEXT: ; return to shader part epilog
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2018-12-06 22:33:40 +08:00
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%x = shl i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: shl_or_vgpr_all2:
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; VI: ; %bb.0:
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; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
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; VI-NEXT: v_or_b32_e32 v0, v2, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: shl_or_vgpr_all2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, v2
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; GFX9-NEXT: ; return to shader part epilog
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2019-05-10 08:09:01 +08:00
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;
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; GFX10-LABEL: shl_or_vgpr_all2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, v2
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2019-06-20 23:08:34 +08:00
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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2019-05-10 08:09:01 +08:00
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; GFX10-NEXT: ; return to shader part epilog
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2018-12-06 22:33:40 +08:00
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%x = shl i32 %a, %b
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%result = or i32 %c, %x
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
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; VI-LABEL: shl_or_vgpr_ac:
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; VI: ; %bb.0:
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; VI-NEXT: v_lshlrev_b32_e32 v0, s2, v0
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: shl_or_vgpr_ac:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_lshl_or_b32 v0, v0, s2, v1
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; GFX9-NEXT: ; return to shader part epilog
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2019-05-10 08:09:01 +08:00
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;
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; GFX10-LABEL: shl_or_vgpr_ac:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_or_b32 v0, v0, s2, v1
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2019-06-20 23:08:34 +08:00
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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2019-05-10 08:09:01 +08:00
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; GFX10-NEXT: ; return to shader part epilog
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2018-12-06 22:33:40 +08:00
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%x = shl i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
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; VI-LABEL: shl_or_vgpr_const:
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; VI: ; %bb.0:
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; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
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; VI-NEXT: v_or_b32_e32 v0, 6, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: shl_or_vgpr_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, 6
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; GFX9-NEXT: ; return to shader part epilog
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2019-05-10 08:09:01 +08:00
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;
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; GFX10-LABEL: shl_or_vgpr_const:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, 6
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2019-06-20 23:08:34 +08:00
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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2019-05-10 08:09:01 +08:00
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; GFX10-NEXT: ; return to shader part epilog
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2018-12-06 22:33:40 +08:00
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%x = shl i32 %a, %b
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%result = or i32 %x, 6
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) {
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; VI-LABEL: shl_or_vgpr_const2:
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; VI: ; %bb.0:
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; VI-NEXT: v_lshlrev_b32_e32 v0, 6, v0
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: shl_or_vgpr_const2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_lshl_or_b32 v0, v0, 6, v1
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; GFX9-NEXT: ; return to shader part epilog
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2019-05-10 08:09:01 +08:00
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;
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; GFX10-LABEL: shl_or_vgpr_const2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_or_b32 v0, v0, 6, v1
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2019-06-20 23:08:34 +08:00
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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2019-05-10 08:09:01 +08:00
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; GFX10-NEXT: ; return to shader part epilog
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2018-12-06 22:33:40 +08:00
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%x = shl i32 %a, 6
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%result = or i32 %x, %b
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) {
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; VI-LABEL: shl_or_vgpr_const_scalar1:
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; VI: ; %bb.0:
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; VI-NEXT: s_lshl_b32 s0, s2, 6
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; VI-NEXT: v_or_b32_e32 v0, s0, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: shl_or_vgpr_const_scalar1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_lshl_or_b32 v0, s2, 6, v0
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; GFX9-NEXT: ; return to shader part epilog
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2019-05-10 08:09:01 +08:00
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;
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; GFX10-LABEL: shl_or_vgpr_const_scalar1:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_or_b32 v0, s2, 6, v0
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2019-06-20 23:08:34 +08:00
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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2019-05-10 08:09:01 +08:00
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; GFX10-NEXT: ; return to shader part epilog
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2018-12-06 22:33:40 +08:00
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%x = shl i32 %a, 6
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%result = or i32 %x, %b
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) {
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; VI-LABEL: shl_or_vgpr_const_scalar2:
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; VI: ; %bb.0:
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; VI-NEXT: v_lshlrev_b32_e32 v0, 6, v0
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; VI-NEXT: v_or_b32_e32 v0, s2, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: shl_or_vgpr_const_scalar2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_lshl_or_b32 v0, v0, 6, s2
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; GFX9-NEXT: ; return to shader part epilog
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2019-05-10 08:09:01 +08:00
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;
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; GFX10-LABEL: shl_or_vgpr_const_scalar2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_lshl_or_b32 v0, v0, 6, s2
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2019-06-20 23:08:34 +08:00
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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2019-05-10 08:09:01 +08:00
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; GFX10-NEXT: ; return to shader part epilog
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2018-12-06 22:33:40 +08:00
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%x = shl i32 %a, 6
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%result = or i32 %x, %b
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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