forked from OSchip/llvm-project
90 lines
4.7 KiB
Plaintext
90 lines
4.7 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
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---
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name: uadde_s32_s1_sss
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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; WAVE64-LABEL: name: uadde_s32_s1_sss
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE64: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; WAVE64: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; WAVE64: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; WAVE64: $scc = COPY [[COPY3]]
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; WAVE64: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY]], [[COPY1]], implicit-def $scc, implicit $scc
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; WAVE64: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
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; WAVE64: $scc = COPY [[COPY4]]
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; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
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; WAVE64: S_ENDPGM 0, implicit [[S_ADDC_U32_]], implicit [[S_CSELECT_B32_]]
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; WAVE32-LABEL: name: uadde_s32_s1_sss
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; WAVE32: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; WAVE32: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; WAVE32: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
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; WAVE32: $scc = COPY [[COPY3]]
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; WAVE32: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY]], [[COPY1]], implicit-def $scc, implicit $scc
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; WAVE32: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
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; WAVE32: $scc = COPY [[COPY4]]
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; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
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; WAVE32: S_ENDPGM 0, implicit [[S_ADDC_U32_]], implicit [[S_CSELECT_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:sgpr(s32) = G_ICMP intpred(eq), %2, %3
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%5:sgpr(s32), %6:sgpr(s32) = G_UADDE %0, %1, %4
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%7:sgpr(s32) = G_SELECT %6, %0, %1
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S_ENDPGM 0, implicit %5, implicit %7
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...
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---
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name: uadde_s32_s1_vvv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; WAVE64-LABEL: name: uadde_s32_s1_vvv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
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; WAVE64: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
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; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_ADDC_U32_e64_1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
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; WAVE32-LABEL: name: uadde_s32_s1_vvv
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
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; WAVE32: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
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; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_ADDC_U32_e64_1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = COPY $vgpr2
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%3:vgpr(s32) = G_CONSTANT i32 0
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%4:vcc(s1) = G_ICMP intpred(eq), %2, %3
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%5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4
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%7:vgpr(s32) = G_SELECT %6, %0, %1
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S_ENDPGM 0, implicit %5, implicit %7
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...
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