2019-09-09 06:11:51 +08:00
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: mul_u24_vsv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: mul_u24_vsv
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; GCN: liveins: $sgpr0, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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2020-05-22 18:54:59 +08:00
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; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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2019-09-09 06:11:51 +08:00
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; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: mul_u24_vvs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: mul_u24_vvs
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; GCN: liveins: $sgpr0, $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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2020-05-22 18:54:59 +08:00
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; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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2019-09-09 06:11:51 +08:00
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; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: mul_u24_vvv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: mul_u24_vvv
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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2020-05-22 18:54:59 +08:00
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; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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2019-09-09 06:11:51 +08:00
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; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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