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llvm-project/llvm/test/CodeGen/X86/legalize-shl-vec.ll

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[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=X64
Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
define <2 x i256> @test_shl(<2 x i256> %In) {
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-LABEL: test_shl:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X32: # %bb.0:
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: shldl $2, %edx, %ecx
; X32-NEXT: movl %ecx, 60(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: shldl $2, %ecx, %edx
; X32-NEXT: movl %edx, 56(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: shldl $2, %edx, %ecx
; X32-NEXT: movl %ecx, 52(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: shldl $2, %ecx, %edx
; X32-NEXT: movl %edx, 48(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: shldl $2, %edx, %ecx
; X32-NEXT: movl %ecx, 44(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: shldl $2, %ecx, %edx
; X32-NEXT: movl %edx, 40(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: shldl $2, %edx, %ecx
; X32-NEXT: movl %ecx, 36(%eax)
; X32-NEXT: shll $2, %edx
; X32-NEXT: movl %edx, 32(%eax)
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: movl $0, 28(%eax)
; X32-NEXT: movl $0, 24(%eax)
; X32-NEXT: movl $0, 20(%eax)
; X32-NEXT: movl $0, 16(%eax)
; X32-NEXT: movl $0, 12(%eax)
; X32-NEXT: movl $0, 8(%eax)
; X32-NEXT: movl $0, 4(%eax)
; X32-NEXT: movl $0, (%eax)
; X32-NEXT: retl $4
;
; X64-LABEL: test_shl:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; X64-NEXT: shldq $2, %rax, %rcx
; X64-NEXT: shldq $2, %rdx, %rax
; X64-NEXT: shldq $2, %r9, %rdx
; X64-NEXT: shlq $2, %r9
; X64-NEXT: movq %rcx, 56(%rdi)
; X64-NEXT: movq %rax, 48(%rdi)
; X64-NEXT: movq %rdx, 40(%rdi)
; X64-NEXT: movq %r9, 32(%rdi)
[X86][DAG] Switch X86 Target to post-legalized store merge Move store merge to happen after intrinsic lowering to allow lowered stores to be merged. Some regressions due in MergeConsecutiveStores to missing insert_subvector that are addressed in follow up patch. Reviewers: craig.topper, efriedma, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34559 llvm-svn: 310710
2017-08-11 21:21:35 +08:00
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 16(%rdi)
; X64-NEXT: movaps %xmm0, (%rdi)
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
%Amt = insertelement <2 x i256> <i256 1, i256 2>, i256 -1, i32 0
Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
%Out = shl <2 x i256> %In, %Amt
ret <2 x i256> %Out
}
define <2 x i256> @test_srl(<2 x i256> %In) {
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-LABEL: test_srl:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X32: # %bb.0:
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: pushl %ebx
; X32-NEXT: .cfi_def_cfa_offset 12
; X32-NEXT: pushl %edi
; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 20
; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_def_cfa_offset 28
; X32-NEXT: .cfi_offset %esi, -20
; X32-NEXT: .cfi_offset %edi, -16
; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: shldl $28, %eax, %ecx
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: shldl $28, %esi, %eax
; X32-NEXT: movl %eax, (%esp) # 4-byte Spill
; X32-NEXT: shldl $28, %edi, %esi
; X32-NEXT: shldl $28, %ebx, %edi
; X32-NEXT: shldl $28, %ebp, %ebx
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X32-NEXT: shldl $28, %eax, %ebp
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: shrdl $4, %eax, %ecx
; X32-NEXT: shrl $4, %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl %edx, 60(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx # 4-byte Reload
; X32-NEXT: movl %edx, 56(%eax)
; X32-NEXT: movl (%esp), %edx # 4-byte Reload
; X32-NEXT: movl %edx, 52(%eax)
; X32-NEXT: movl %esi, 48(%eax)
; X32-NEXT: movl %edi, 44(%eax)
; X32-NEXT: movl %ebx, 40(%eax)
; X32-NEXT: movl %ebp, 36(%eax)
; X32-NEXT: movl %ecx, 32(%eax)
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: movl $0, 28(%eax)
; X32-NEXT: movl $0, 24(%eax)
; X32-NEXT: movl $0, 20(%eax)
; X32-NEXT: movl $0, 16(%eax)
; X32-NEXT: movl $0, 12(%eax)
; X32-NEXT: movl $0, 8(%eax)
; X32-NEXT: movl $0, 4(%eax)
; X32-NEXT: movl $0, (%eax)
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X32-NEXT: addl $8, %esp
; X32-NEXT: popl %esi
; X32-NEXT: popl %edi
; X32-NEXT: popl %ebx
; X32-NEXT: popl %ebp
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: retl $4
;
; X64-LABEL: test_srl:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; X64-NEXT: shrdq $4, %rdx, %r9
; X64-NEXT: shrdq $4, %rax, %rdx
; X64-NEXT: shrdq $4, %rcx, %rax
; X64-NEXT: shrq $4, %rcx
; X64-NEXT: movq %rcx, 56(%rdi)
; X64-NEXT: movq %rax, 48(%rdi)
; X64-NEXT: movq %rdx, 40(%rdi)
; X64-NEXT: movq %r9, 32(%rdi)
[X86][DAG] Switch X86 Target to post-legalized store merge Move store merge to happen after intrinsic lowering to allow lowered stores to be merged. Some regressions due in MergeConsecutiveStores to missing insert_subvector that are addressed in follow up patch. Reviewers: craig.topper, efriedma, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34559 llvm-svn: 310710
2017-08-11 21:21:35 +08:00
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 16(%rdi)
; X64-NEXT: movaps %xmm0, (%rdi)
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
%Amt = insertelement <2 x i256> <i256 3, i256 4>, i256 -1, i32 0
Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
%Out = lshr <2 x i256> %In, %Amt
ret <2 x i256> %Out
}
define <2 x i256> @test_sra(<2 x i256> %In) {
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-LABEL: test_sra:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X32: # %bb.0:
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: pushl %ebx
; X32-NEXT: .cfi_def_cfa_offset 12
; X32-NEXT: pushl %edi
; X32-NEXT: .cfi_def_cfa_offset 16
; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 20
; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_def_cfa_offset 28
; X32-NEXT: .cfi_offset %esi, -20
; X32-NEXT: .cfi_offset %edi, -16
; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: shldl $26, %eax, %ecx
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: shldl $26, %esi, %eax
; X32-NEXT: movl %eax, (%esp) # 4-byte Spill
; X32-NEXT: shldl $26, %edi, %esi
; X32-NEXT: shldl $26, %ebx, %edi
; X32-NEXT: shldl $26, %ebp, %ebx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shldl $26, %eax, %ebp
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X32-NEXT: shrdl $6, %eax, %ecx
; X32-NEXT: sarl $6, %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl %edx, 60(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx # 4-byte Reload
; X32-NEXT: movl %edx, 56(%eax)
; X32-NEXT: movl (%esp), %edx # 4-byte Reload
; X32-NEXT: movl %edx, 52(%eax)
; X32-NEXT: movl %esi, 48(%eax)
; X32-NEXT: movl %edi, 44(%eax)
; X32-NEXT: movl %ebx, 40(%eax)
; X32-NEXT: movl %ebp, 36(%eax)
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: movl %ecx, 32(%eax)
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: sarl $31, %ecx
; X32-NEXT: movl %ecx, 28(%eax)
; X32-NEXT: movl %ecx, 24(%eax)
; X32-NEXT: movl %ecx, 20(%eax)
; X32-NEXT: movl %ecx, 16(%eax)
; X32-NEXT: movl %ecx, 12(%eax)
; X32-NEXT: movl %ecx, 8(%eax)
; X32-NEXT: movl %ecx, 4(%eax)
; X32-NEXT: movl %ecx, (%eax)
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X32-NEXT: addl $8, %esp
; X32-NEXT: popl %esi
; X32-NEXT: popl %edi
; X32-NEXT: popl %ebx
; X32-NEXT: popl %ebp
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X32-NEXT: retl $4
;
; X64-LABEL: test_sra:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdx
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X64-NEXT: shrdq $6, %rdx, %r9
; X64-NEXT: shrdq $6, %rax, %rdx
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X64-NEXT: sarq $63, %r8
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
; X64-NEXT: shrdq $6, %rcx, %rax
; X64-NEXT: sarq $6, %rcx
; X64-NEXT: movq %rcx, 56(%rdi)
; X64-NEXT: movq %rax, 48(%rdi)
; X64-NEXT: movq %rdx, 40(%rdi)
[X86] Regenerate v2i256 shift legalization tests llvm-svn: 276692
2016-07-26 05:14:22 +08:00
; X64-NEXT: movq %r9, 32(%rdi)
; X64-NEXT: movq %r8, 24(%rdi)
; X64-NEXT: movq %r8, 16(%rdi)
; X64-NEXT: movq %r8, 8(%rdi)
; X64-NEXT: movq %r8, (%rdi)
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
[x86] preserve test intent by removing undef D43141 proposes to correct undef folding in the DAG, and this test would not survive that change. llvm-svn: 324816
2018-02-10 23:28:08 +08:00
%Amt = insertelement <2 x i256> <i256 5, i256 6>, i256 -1, i32 0
Reapply fixed r241790: Fix shift legalization and lowering for big constants. Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
2015-07-09 22:58:04 +08:00
%Out = ashr <2 x i256> %In, %Amt
ret <2 x i256> %Out
}