forked from OSchip/llvm-project
117 lines
3.3 KiB
Plaintext
117 lines
3.3 KiB
Plaintext
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# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
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# Check that SILoadStoreOptimizer honors physregs defs/uses between moved
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# instructions.
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#
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# The following IR snippet would usually be optimized by the peephole optimizer.
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# However, an equivalent situation can occur with buffer instructions as well.
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# CHECK-LABEL: name: scc_def_and_use_no_dependency
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# CHECK: S_ADD_U32
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# CHECK: S_ADDC_U32
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# CHECK: DS_READ2_B32
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--- |
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define amdgpu_kernel void @scc_def_and_use_no_dependency(i32 addrspace(3)* %ptr.0) nounwind {
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%ptr.4 = getelementptr i32, i32 addrspace(3)* %ptr.0, i32 1
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%ptr.64 = getelementptr i32, i32 addrspace(3)* %ptr.0, i32 16
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ret void
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}
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define amdgpu_kernel void @scc_def_and_use_dependency(i32 addrspace(3)* %ptr.0) nounwind {
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%ptr.4 = getelementptr i32, i32 addrspace(3)* %ptr.0, i32 1
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%ptr.64 = getelementptr i32, i32 addrspace(3)* %ptr.0, i32 16
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ret void
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}
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...
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---
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name: scc_def_and_use_no_dependency
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: false
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liveins:
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- { reg: '$vgpr0' }
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- { reg: '$sgpr0' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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%1:vgpr_32 = COPY $vgpr0
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%10:sgpr_32 = COPY $sgpr0
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$m0 = S_MOV_B32 -1
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%2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.0)
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%11:sgpr_32 = S_ADD_U32 %10, 4, implicit-def $scc
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%12:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
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%3:vgpr_32 = DS_READ_B32 %1, 64, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.64)
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S_ENDPGM
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...
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# CHECK-LABEL: name: scc_def_and_use_dependency
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# CHECK: DS_READ2_B32
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# CHECK: S_ADD_U32
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# CHECK: S_ADDC_U32
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---
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name: scc_def_and_use_dependency
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: false
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liveins:
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- { reg: '$vgpr0' }
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- { reg: '$sgpr0' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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%1:vgpr_32 = COPY $vgpr0
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%10:sgpr_32 = COPY $sgpr0
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$m0 = S_MOV_B32 -1
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%2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.0)
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%20:sgpr_32 = V_READFIRSTLANE_B32 %2, implicit $exec
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%21:sgpr_32 = S_ADD_U32 %20, 4, implicit-def $scc
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; The S_ADDC_U32 depends on the first DS_READ_B32 only via SCC
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%11:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
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%3:vgpr_32 = DS_READ_B32 %1, 64, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.64)
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S_ENDPGM
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...
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