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llvm-project/llvm/test/CodeGen/X86/ghc-cc.ll

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add support, testcases, and dox for the new GHC calling convention. Patch by David Terei! llvm-svn: 98212
2010-03-11 08:22:57 +08:00
; RUN: llc < %s -tailcallopt -mtriple=i686-linux-gnu | FileCheck %s
; Test the GHC call convention works (x86-32)
[CodeGen] Print register names in lowercase in both MIR and debug output As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
2017-11-29 01:15:09 +08:00
@base = external global i32 ; assigned to register: ebx
@sp = external global i32 ; assigned to register: ebp
@hp = external global i32 ; assigned to register: edi
@r1 = external global i32 ; assigned to register: esi
add support, testcases, and dox for the new GHC calling convention. Patch by David Terei! llvm-svn: 98212
2010-03-11 08:22:57 +08:00
define void @zap(i32 %a, i32 %b) nounwind {
entry:
; CHECK: movl {{[0-9]*}}(%esp), %ebx
; CHECK-NEXT: movl {{[0-9]*}}(%esp), %ebp
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly named "callq", so this only impacted x86-32. This fixes rdar://8456370 - llvm-mc rejects 'calll' This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call, I will file a bugzilla. llvm-svn: 114534
2010-09-22 13:49:14 +08:00
; CHECK-NEXT: calll addtwo
Parse 'ghccc' in .ll files as the GHC convention (cc 10) Previously we just used "cc 10" in the .ll files, but that isn't very human readable. llvm-svn: 223076
2014-12-02 05:04:44 +08:00
%0 = call ghccc i32 @addtwo(i32 %a, i32 %b)
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly named "callq", so this only impacted x86-32. This fixes rdar://8456370 - llvm-mc rejects 'calll' This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call, I will file a bugzilla. llvm-svn: 114534
2010-09-22 13:49:14 +08:00
; CHECK: calll foo
add support, testcases, and dox for the new GHC calling convention. Patch by David Terei! llvm-svn: 98212
2010-03-11 08:22:57 +08:00
call void @foo() nounwind
ret void
}
Parse 'ghccc' in .ll files as the GHC convention (cc 10) Previously we just used "cc 10" in the .ll files, but that isn't very human readable. llvm-svn: 223076
2014-12-02 05:04:44 +08:00
define ghccc i32 @addtwo(i32 %x, i32 %y) nounwind {
add support, testcases, and dox for the new GHC calling convention. Patch by David Terei! llvm-svn: 98212
2010-03-11 08:22:57 +08:00
entry:
; CHECK: leal (%ebx,%ebp), %eax
%0 = add i32 %x, %y
; CHECK-NEXT: ret
ret i32 %0
}
Parse 'ghccc' in .ll files as the GHC convention (cc 10) Previously we just used "cc 10" in the .ll files, but that isn't very human readable. llvm-svn: 223076
2014-12-02 05:04:44 +08:00
define ghccc void @foo() nounwind {
add support, testcases, and dox for the new GHC calling convention. Patch by David Terei! llvm-svn: 98212
2010-03-11 08:22:57 +08:00
entry:
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; CHECK: movl r1, %esi
Revert "Temporarily enable MI-Sched on X86." This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823
2013-06-25 10:48:58 +08:00
; CHECK-NEXT: movl hp, %edi
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; CHECK-NEXT: movl sp, %ebp
; CHECK-NEXT: movl base, %ebx
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @r1
%1 = load i32, i32* @hp
%2 = load i32, i32* @sp
%3 = load i32, i32* @base
add support, testcases, and dox for the new GHC calling convention. Patch by David Terei! llvm-svn: 98212
2010-03-11 08:22:57 +08:00
; CHECK: jmp bar
Parse 'ghccc' in .ll files as the GHC convention (cc 10) Previously we just used "cc 10" in the .ll files, but that isn't very human readable. llvm-svn: 223076
2014-12-02 05:04:44 +08:00
tail call ghccc void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind
add support, testcases, and dox for the new GHC calling convention. Patch by David Terei! llvm-svn: 98212
2010-03-11 08:22:57 +08:00
ret void
}
Parse 'ghccc' in .ll files as the GHC convention (cc 10) Previously we just used "cc 10" in the .ll files, but that isn't very human readable. llvm-svn: 223076
2014-12-02 05:04:44 +08:00
declare ghccc void @bar(i32, i32, i32, i32)