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llvm-project/llvm/test/CodeGen/Hexagon/vextract-basic.mir

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[Hexagon] Replace multiple vector extracts with store-load combinations llvm-svn: 323561
2018-01-27 05:17:14 +08:00
# RUN: llc -march=hexagon -mattr=+hvx,+hvx-length64b -run-pass hexagon-vextract %s -o - | FileCheck %s
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r0, $r1, $v0
%0:hvxvr = COPY $v0
%1:intregs = COPY $r0
%2:intregs = COPY $r1
[Hexagon] Replace multiple vector extracts with store-load combinations llvm-svn: 323561
2018-01-27 05:17:14 +08:00
%3:intregs = A2_tfrsi 5
%4:intregs = V6_extractw %0, %1
; CHECK: %[[A0:[0-9]+]]:intregs = A2_andir %{{[0-9]+}}, -4
; CHECK: L4_loadri_rr %{{[0-9]+}}, %[[A0]], 0
%5:intregs = V6_extractw %0, %2
; CHECK: %[[A1:[0-9]+]]:intregs = A2_andir %{{[0-9]+}}, -4
; CHECK: L4_loadri_rr %{{[0-9]+}}, %[[A1]], 0
%6:intregs = V6_extractw %0, %3
; Make sure the offset is 4, not 5.
; CHECK: L2_loadri_io %{{[0-9]+}}, 4
...