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llvm-project/llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt

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[AArch64] Add ARMv8.2-A UAO PSTATE bit ARMv8.2-A adds a new PSTATE bit, PSTATE.UAO, which allows the LDTR/STTR instructions to behave the same as LDR/STR with respect to execute-only pages at higher privilege levels. New variants of the MSR/MRS instructions are added to allow reading and writing this bit. It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15020 llvm-svn: 254157
2015-11-26 23:32:30 +08:00
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s 2>&1 | FileCheck --check-prefix=NO_V82A %s
[0x7f,0x40,0x00,0xd5]
[0x7f,0x41,0x00,0xd5]
[0x7f,0x42,0x00,0xd5]
# CHECK: msr UAO, #0
# CHECK: msr UAO, #1
# CHECK: msr S0_0_C4_C2_3, xzr
# NO_V82A: msr S0_0_C4_C0_3, xzr
# NO_V82A: msr S0_0_C4_C1_3, xzr
# NO_V82A: msr S0_0_C4_C2_3, xzr
[0x81,0x42,0x18,0xd5]
[0x82,0x42,0x38,0xd5]
# CHECK: msr UAO, x1
# CHECK: mrs x2, UAO
# NO_V82A: msr S3_0_C4_C2_4, x1
# NO_V82A: mrs x2, S3_0_C4_C2_4