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llvm-project/llvm/lib/Target/ARM/ARM.td

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 06:18:28 +08:00
//
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 06:18:28 +08:00
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. llvm-svn: 59953
2008-11-24 15:34:46 +08:00
include "llvm/Target/Target.td"
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 06:18:28 +08:00
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
//===----------------------------------------------------------------------===//
// ARM Helper classes.
//
class ProcNoItin<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
class Architecture<string fname, string aname, list<SubtargetFeature> features >
: SubtargetFeature<fname, "ARMArch", aname,
!strconcat(aname, " architecture"), features>;
Sink feature IsThumb into MC layer. llvm-svn: 134608
2011-07-07 16:26:46 +08:00
//===----------------------------------------------------------------------===//
// ARM Subtarget state.
//
Rename attribute 'thumb' to a more descriptive 'thumb-mode'. llvm-svn: 134626
2011-07-08 03:05:12 +08:00
def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
Sink feature IsThumb into MC layer. llvm-svn: 134608
2011-07-07 16:26:46 +08:00
"Thumb mode">;
Nuke it from orbit. It's the only way to be sure. (Kill the dead non-MC asm printer for the ARM target.) llvm-svn: 115127
2010-09-30 09:57:53 +08:00
Migrate existing backends that care about software floating point to use the information in the module rather than TargetOptions. We've had and clang has used the use-soft-float attribute for some time now so have the backends set a subtarget feature based on a particular function now that subtargets are created based on functions and function attributes. For the one middle end soft float check go ahead and create an overloadable TargetLowering::useSoftFloat function that just checks the TargetSubtargetInfo in all cases. Also remove the command line option that hard codes whether or not soft-float is set by using the attribute for all of the target specific test cases - for the generic just go ahead and add the attribute in the one case that showed up. llvm-svn: 237079
2015-05-12 09:26:05 +08:00
def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
"Use software floating point features.">;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 15:51:42 +08:00
//===----------------------------------------------------------------------===//
// ARM Subtarget features.
//
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
Add placeholder for thumb2 stuff llvm-svn: 72593
2009-05-30 07:41:08 +08:00
"Enable VFP2 instructions">;
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
"Enable VFP3 instructions",
[FeatureVFP2]>;
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
"Enable NEON instructions",
[FeatureVFP3]>;
Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. llvm-svn: 134569
2011-07-07 08:08:19 +08:00
def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
Add placeholder for thumb2 stuff llvm-svn: 72593
2009-05-30 07:41:08 +08:00
"Enable Thumb2 instructions">;
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. llvm-svn: 110798
2010-08-11 15:17:46 +08:00
def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one. Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 llvm-svn: 183710
2013-06-11 07:20:58 +08:00
"Does not support ARM mode execution",
[ModeThumb]>;
Add substarget feature for FP16 llvm-svn: 98503
2010-03-15 02:42:38 +08:00
def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
"Enable half-precision floating point">;
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
"Enable VFP4 instructions",
[FeatureVFP3, FeatureFP16]>;
[ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options to be more consistent. llvm-svn: 190692
2013-09-13 21:46:57 +08:00
def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
Add a Subtarget feature 'v8fp' to the ARM backend. llvm-svn: 185073
2013-06-27 19:49:26 +08:00
"true", "Enable ARMv8 FP",
[FeatureVFP4]>;
[ARM] Add subtarget features for ARMv8.2-A This adds subtarget features for ARMv8.2-A, which builds on (and requires the features from) ARMv8.1-A. Most assembler-visible features of ARMv8.2-A are system instructions, and are all required parts of the architecture, so just depend on the HasV8_2aOps subtarget feature. There is also one large, optional feature, which adds 16-bit floating point versions of all existing floating-point instructions (VFP and SIMD), this is represented by the FeatureFullFP16 subtarget feature. Differential Revision: http://reviews.llvm.org/D15036 llvm-svn: 254399
2015-12-01 18:23:06 +08:00
def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
"Enable full half-precision floating point",
[FeatureFPARMv8]>;
PR8359: The ARM backend may end up allocating registers D16 to D31 when "-mattr=+vfp3" is specified. However, this will not work for hardware that only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16". Patch by Jan Voung! llvm-svn: 116310
2010-10-13 00:22:47 +08:00
def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Restrict FP to 16 double registers">;
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack instructions to subtarget features and update tests to reflect. PR5717. llvm-svn: 103136
2010-05-06 07:44:43 +08:00
def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
"Enable divide instructions">;
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
"HasHardwareDivideInARM", "true",
"Enable divide instructions in ARM mode">;
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) llvm-svn: 110795
2010-08-11 14:51:54 +08:00
def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack instructions to subtarget features and update tests to reflect. PR5717. llvm-svn: 103136
2010-05-06 07:44:43 +08:00
"Enable Thumb2 extract and pack instructions">;
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) llvm-svn: 110795
2010-08-11 14:51:54 +08:00
def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
"Has data barrier (dmb / dsb) instructions">;
[ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate features llvm-svn: 257877
2016-01-15 18:23:46 +08:00
def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
"Has v7 clrex instruction">;
def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
"HasAcquireRelease", "true",
"Has v8 acquire/release (lda/ldaex etc) instructions">;
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles). llvm-svn: 108256
2010-07-14 03:21:50 +08:00
def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
"FP compare + branch is slow">;
cortex m4 has floating point support, but only single precision. llvm-svn: 110810
2010-08-11 23:44:15 +08:00
def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
"Floating point unit supports single precision only">;
ARM: Add Performance Monitor Extensions feature Performance monitors, including a basic cycle counter, are an official extension in the ARMv7 specification. This adds support for enabling and disabling them, orthogonally from CPU selection. rdar://problem/13939186 llvm-svn: 182602
2013-05-24 03:11:14 +08:00
def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
"Enable support for Performance Monitor extensions">;
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
2013-04-10 20:08:35 +08:00
def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
"Enable support for TrustZone security extensions">;
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
"Enable support for Cryptography extensions",
[FeatureNEON]>;
ARM: Add subtarget feature for CRC Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 llvm-svn: 193599
2013-10-29 17:47:35 +08:00
def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
"Enable support for CRC instructions">;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 15:51:42 +08:00
ARM: add cyclone CPU with ZeroCycleZeroing feature. The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
2014-04-01 21:22:02 +08:00
// Cyclone has preferred instructions for zeroing VFP registers, which can
// execute in 0 cycles.
def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
"Has zero-cycle zeroing instructions">;
Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
2010-12-06 06:04:16 +08:00
// Some processors have FP multiply-accumulate instructions that don't
// play nicely with other VFP / NEON instructions, and it's generally better
switch the use-vml[as] instructions flag to a subtarget 'feature' llvm-svn: 99565
2010-03-26 07:11:16 +08:00
// to just not use them.
Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
2010-12-06 06:04:16 +08:00
def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
"Disable VFP / NEON MAC instructions">;
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 llvm-svn: 128665
2011-04-01 03:38:48 +08:00
// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
"HasVMLxForwarding", "true",
"Has multiplier accumulator forwarding">;
switch the flag for using NEON for SP floating point to a subtarget 'feature'. Re-commit. This time complete with testsuite updates. llvm-svn: 99570
2010-03-26 07:47:34 +08:00
// Some processors benefit from using NEON instructions for scalar
// single-precision FP operations.
80 column cleanup. llvm-svn: 111266
2010-08-18 02:39:16 +08:00
def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
"true",
"Use NEON for single precision FP">;
switch the flag for using NEON for SP floating point to a subtarget 'feature'. Re-commit. This time complete with testsuite updates. llvm-svn: 99570
2010-03-26 07:47:34 +08:00
Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations. llvm-svn: 110584
2010-08-10 02:35:19 +08:00
// Disable 32-bit to 16-bit narrowing for experimentation.
def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
"Prefer 32-bit Thumb instrs">;
switch the use-vml[as] instructions flag to a subtarget 'feature' llvm-svn: 99565
2010-03-26 07:11:16 +08:00
Avoid some 's' 16-bit instruction which partially update CPSR (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 llvm-svn: 129773
2011-04-20 02:11:49 +08:00
/// Some instructions update CPSR partially, which can add false dependency for
/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
/// mapped to a separate physical register. Avoid partial CPSR update for these
/// processors.
def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
"AvoidCPSRPartialUpdate", "true",
"Avoid CPSR partial update for OOO execution">;
On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr, are more expensive than the non-flag setting variant. Teach thumb2 size reduction pass to avoid generating them unless we are optimizing for size. rdar://12892707 llvm-svn: 170728
2012-12-21 03:59:30 +08:00
def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
"AvoidMOVsShifterOperand", "true",
"Avoid movs instructions with shifter operand">;
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. llvm-svn: 151645
2012-02-29 02:51:51 +08:00
// Some processors perform return stack prediction. CodeGen should avoid issue
// "normal" call instructions to callees which do not return.
def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
"Has return address stack">;
[ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-dev llvm-svn: 251125
2015-10-24 01:19:19 +08:00
/// DSP extension.
def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following a revert of r248152 and new review comments, this patch also includes renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc. The spelling of "t2dsp" is preserved, pending a further investigation of its possible external usage. Differential Revision: http://reviews.llvm.org/D12937 llvm-svn: 248519
2015-09-25 01:31:16 +08:00
"Supports DSP instructions in ARM and/or Thumb2">;
ARMv7M vs. ARMv7E-M support. The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 llvm-svn: 134261
2011-07-02 05:12:19 +08:00
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160
2010-11-03 14:34:55 +08:00
// Multiprocessing extension.
def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
"Supports Multiprocessing extension">;
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) llvm-svn: 110795
2010-08-11 14:51:54 +08:00
[ARM] Add Virtualization subtarget feature and more build attributes in this area Add a Virtualization ARM subtarget feature along with adding proper build attribute emission for Tag_Virtualization_use (encodes Virtualization and TrustZone) and Tag_MPextension_use. Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to something that is more maintainable. This changes the focus of this testcase away from testing CPU defaults (which is tested elsewhere), onto specifically testing that attributes are encoded correctly. llvm-svn: 193859
2013-11-01 21:27:35 +08:00
// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
def FeatureVirtualization : SubtargetFeature<"virtualization",
"HasVirtualization", "true",
"Supports Virtualization extension",
[FeatureHWDiv, FeatureHWDivARM]>;
[ARM] Split A/R class into separate subtarget features. Patch by Bradley Smith. llvm-svn: 191202
2013-09-23 22:26:15 +08:00
// M-series ISA
def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
2011-09-28 22:21:38 +08:00
"Is microcontroller profile ('M' series)">;
[ARM] Split A/R class into separate subtarget features. Patch by Bradley Smith. llvm-svn: 191202
2013-09-23 22:26:15 +08:00
// R-series ISA
def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
"Is realtime profile ('R' series)">;
// A-series ISA
def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
"Is application profile ('A' series)">;
Add a special ARM trap encoding for NaCl. More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
2013-01-31 00:30:19 +08:00
// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
// See ARMInstrInfo.td for details.
def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
"NaCl trap">;
[ARM] Define subtarget feature strict-align. This commit defines subtarget feature strict-align and uses it instead of cl::opt -arm-strict-align to decide whether strict alignment should be forced. Also, remove the logic that was checking the OS and architecture as clang is now responsible for setting strict-align based on the command line options specified and the target architecute and OS. rdar://problem/21529937 http://reviews.llvm.org/D11470 llvm-svn: 243493
2015-07-29 06:44:28 +08:00
def FeatureStrictAlign : SubtargetFeature<"strict-align",
"StrictAlign", "true",
"Disallow all unaligned memory "
"access">;
[ARM] Define a subtarget feature and use it to decide whether long calls should be emitted. This is needed to enable ARM long calls for LTO and enable and disable it on a per-function basis. Out-of-tree projects currently using EnableARMLongCalls to emit long calls should start passing "+long-calls" to the feature string (see the changes made to clang in r241565). rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D9364 llvm-svn: 241566
2015-07-07 14:54:42 +08:00
def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
"Generate calls via indirect call "
"instructions">;
[ARM] Define subtarget feature "reserve-r9", which is used to decide whether register r9 should be reserved. This recommits r242737, which broke bots because the number of subtarget features went over the limit of 64. This change is needed because we cannot use a backend option to set cl::opt "arm-reserve-r9" when doing LTO. Out-of-tree projects currently using cl::opt option "-arm-reserve-r9" to reserve r9 should make changes to add subtarget feature "reserve-r9" to the IR. rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11320 llvm-svn: 242756
2015-07-21 09:42:02 +08:00
def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
"Reserve R9, making it unavailable as "
"GPR">;
[ARM] Define a subtarget feature that is used to avoid using movt/movw pairs for 32-bit immediates. This change is needed to avoid emitting movt/movw pairs when doing LTO and do so on a per-function basis. Out-of-tree projects currently using cl::opt option -arm-use-movt=0 or false to avoid emitting movt/movw pairs should make changes to add subtarget feature "+no-movt" (see the changes made to clang in r242368). rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11026 llvm-svn: 242369
2015-07-16 08:58:23 +08:00
def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
"Don't use movt/movw pairs for 32-bit "
"imms">;
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
//===----------------------------------------------------------------------===//
// ARM ISAa.
//
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
Sink feature IsThumb into MC layer. llvm-svn: 134608
2011-07-07 16:26:46 +08:00
"Support ARM v4T instructions">;
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
Sink feature IsThumb into MC layer. llvm-svn: 134608
2011-07-07 16:26:46 +08:00
"Support ARM v5T instructions",
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
[HasV4TOps]>;
def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
Sink feature IsThumb into MC layer. llvm-svn: 134608
2011-07-07 16:26:46 +08:00
"Support ARM v5TE, v5TEj, and v5TExp instructions",
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
[HasV5TOps]>;
def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
Sink feature IsThumb into MC layer. llvm-svn: 134608
2011-07-07 16:26:46 +08:00
"Support ARM v6 instructions",
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
[HasV5TEOps]>;
ARM: allow cortex-m0 to use hint instructions The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
2013-10-07 19:10:47 +08:00
def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
"Support ARM v6M instructions",
[HasV6Ops]>;
[ARM] Add support for ARMV6K subtarget (LLVM) ARMv6K is another layer between ARMV6 and ARMV6T2. This is the LLVM side of the changes. ARMV6 family LLVM implementation. +-------------------------------------+ | ARMV6 | +----------------+--------------------+ | ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors +----------------+--------------------+ have support for hint instructions | ARMV6T2 (arm,thumb,thumb2) | (SEV/WFE/WFI/NOP/YIELD). They can +-------------------------------------+ be either real or default to NOP. | ARMV7 (arm,thumb,thumb2) | The two processors also use +-------------------------------------+ different encoding for them. Patch by Vinicius Tinti. llvm-svn: 232468
2015-03-17 19:55:28 +08:00
def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
"Support ARM v6k instructions",
[HasV6Ops]>;
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
Sink feature IsThumb into MC layer. llvm-svn: 134608
2011-07-07 16:26:46 +08:00
"Support ARM v6t2 instructions",
[ARM] Add support for ARMV6K subtarget (LLVM) ARMv6K is another layer between ARMV6 and ARMV6T2. This is the LLVM side of the changes. ARMV6 family LLVM implementation. +-------------------------------------+ | ARMV6 | +----------------+--------------------+ | ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors +----------------+--------------------+ have support for hint instructions | ARMV6T2 (arm,thumb,thumb2) | (SEV/WFE/WFI/NOP/YIELD). They can +-------------------------------------+ be either real or default to NOP. | ARMV7 (arm,thumb,thumb2) | The two processors also use +-------------------------------------+ different encoding for them. Patch by Vinicius Tinti. llvm-svn: 232468
2015-03-17 19:55:28 +08:00
[HasV6MOps, HasV6KOps, FeatureThumb2]>;
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
Sink feature IsThumb into MC layer. llvm-svn: 134608
2011-07-07 16:26:46 +08:00
"Support ARM v7 instructions",
[ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate features llvm-svn: 257877
2016-01-15 18:23:46 +08:00
[HasV6T2Ops, FeaturePerfMon,
FeatureV7Clrex]>;
Add a subtarget feature 'v8' to the ARM backend. This allows for targeting the ARMv8 AArch32 variant. llvm-svn: 184967
2013-06-27 00:58:26 +08:00
def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
"Support ARM v8 instructions",
[ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate features llvm-svn: 257877
2016-01-15 18:23:46 +08:00
[HasV7Ops, FeatureAcquireRelease]>;
[ARM] Rename v8.1a from "extension" to "architecture" v8.1a is renamed to architecture, following current entity naming approach. Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8767 llvm-svn: 233811
2015-04-01 22:54:56 +08:00
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
[AArch64, ARM] Add v8.1a architecture and generic cpu New architecture and cpu added, following http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8505 llvm-svn: 233290
2015-03-27 01:05:54 +08:00
"Support ARM v8.1a instructions",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
[HasV8Ops]>;
[ARM] Add subtarget features for ARMv8.2-A This adds subtarget features for ARMv8.2-A, which builds on (and requires the features from) ARMv8.1-A. Most assembler-visible features of ARMv8.2-A are system instructions, and are all required parts of the architecture, so just depend on the HasV8_2aOps subtarget feature. There is also one large, optional feature, which adds 16-bit floating point versions of all existing floating-point instructions (VFP and SIMD), this is represented by the FeatureFullFP16 subtarget feature. Differential Revision: http://reviews.llvm.org/D15036 llvm-svn: 254399
2015-12-01 18:23:06 +08:00
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
"Support ARM v8.2a instructions",
[HasV8_1aOps]>;
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) llvm-svn: 110795
2010-08-11 14:51:54 +08:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 15:51:42 +08:00
//===----------------------------------------------------------------------===//
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
// ARM Processor subtarget features.
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 15:51:42 +08:00
//
Add cortex-a5 subtarget to the supported ARM architectures llvm-svn: 168933
2012-11-30 03:48:01 +08:00
def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-A5 ARM processors", []>;
[ARM] add basic Cortex-A7 support to LLVM backend llvm-svn: 195358
2013-11-21 22:03:21 +08:00
def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-A7 ARM processors", []>;
Teach if-converter to be more careful with predicating instructions that would take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
2010-09-10 09:29:16 +08:00
def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-A8 ARM processors", []>;
Teach if-converter to be more careful with predicating instructions that would take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
2010-09-10 09:29:16 +08:00
def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-A9 ARM processors", []>;
Add support for Cortex-A12. Patch by Oliver Stannard! llvm-svn: 195448
2013-11-22 19:53:16 +08:00
def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-A12 ARM processors", []>;
def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
"Cortex-A15 ARM processors", []>;
Adds support for the Cortex-A17 to the ARM backend Patch by Matthew Wahab. llvm-svn: 219606
2014-10-13 18:22:19 +08:00
def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-A17 ARM processors", []>;
[AArch64]: Add support for Cortex-A35 Adds support for the new Cortex-A35 ARMv8-A core. llvm-svn: 254503
2015-12-02 19:53:44 +08:00
def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
"Cortex-A35 ARM processors", []>;
Add subtarget feature support for Cortex-A53 Some previous implicit defaults have changed, for example FP and NEON are now on by default. llvm-svn: 192590
2013-10-14 21:16:57 +08:00
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-A53 ARM processors", []>;
Add Cortex-A57 support llvm-svn: 192591
2013-10-14 21:17:07 +08:00
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-A57 ARM processors", []>;
def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
"Cortex-A72 ARM processors", []>;
def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
"Qualcomm ARM processors", []>;
def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
"Swift ARM processors", []>;
Add Cortex-A57 support llvm-svn: 192591
2013-10-14 21:17:07 +08:00
[AArch64] Add support for Samsung Exynos-M1 Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15663 llvm-svn: 256828
2016-01-05 20:51:59 +08:00
def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
"Samsung Exynos-M1 processors", []>;
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
[ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate features llvm-svn: 257877
2016-01-15 18:23:46 +08:00
"Cortex-R4 ARM processors", []>;
Add ARM cortex-r5 subtarget. llvm-svn: 170840
2012-12-21 12:35:05 +08:00
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
"Cortex-R5 ARM processors", []>;
def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
"Cortex-R7 ARM processors", []>;
Added support for mcpu krait - krait processor currently modeled with the same features as A9. - Krait processor additionally has VFP4 (fused multiply add/sub) and hardware division features enabled. - krait has currently the same Schedule model as A9 - krait cpu flag is not recognized by the GNU assembler yet, it is replaced with march=armv7-a to avoid a lower march from being used. llvm-svn: 196619
2013-12-07 06:48:17 +08:00
Make the ARM ABI selectable via SubtargetFeature. This patch makes it possible to select the ABI with -mattr. It will be used to forward clang's -target-abi option to llvm's CodeGen. llvm-svn: 198304
2014-01-02 21:40:08 +08:00
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
//===----------------------------------------------------------------------===//
// ARM schedules.
//
include "ARMSchedule.td"
//===----------------------------------------------------------------------===//
// ARM architectures
//
def ARMv2 : Architecture<"armv2", "ARMv2", []>;
def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
def ARMv3 : Architecture<"armv3", "ARMv3", []>;
def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
def ARMv4 : Architecture<"armv4", "ARMv4", []>;
def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 15:51:42 +08:00
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
FeatureDSP]>;
def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
Handle ARMv6KZ naming Summary: * ARMv6KZ is the "canonical" name, given in the ARMARM * ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM * ARMv6ZK is a popular misspelling, which we should support as an alias. The patch corrects the handling of the names. Functional changes: * ARMv6Z no longer treated as an architecture in its own right * ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias * arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K * default ARMv6K CPU changed to arm1176j-s Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14568 llvm-svn: 253206
2015-11-16 22:05:32 +08:00
def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
Recognize that ARM1176JZ[F]-S support TrustZone Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
2015-10-29 21:56:19 +08:00
FeatureTrustZone]>;
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
FeatureNoARM,
FeatureDB,
FeatureMClass]>;
def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
FeatureNoARM,
FeatureDB,
FeatureMClass]>;
def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
FeatureNEON,
FeatureDB,
FeatureDSP,
FeatureAClass]>;
def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
FeatureDB,
FeatureDSP,
FeatureHWDiv,
FeatureRClass]>;
def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
FeatureThumb2,
FeatureNoARM,
FeatureDB,
FeatureHWDiv,
FeatureMClass]>;
def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
FeatureThumb2,
FeatureNoARM,
FeatureDB,
FeatureHWDiv,
FeatureMClass,
FeatureDSP,
FeatureT2XtPk]>;
def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
FeatureAClass,
FeatureDB,
FeatureFPARMv8,
FeatureNEON,
FeatureDSP,
Recognize that ARM1176JZ[F]-S support TrustZone Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
2015-10-29 21:56:19 +08:00
FeatureTrustZone,
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
FeatureMP,
FeatureVirtualization,
FeatureCrypto,
FeatureCRC]>;
def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
FeatureAClass,
FeatureDB,
FeatureFPARMv8,
FeatureNEON,
FeatureDSP,
FeatureTrustZone,
FeatureMP,
FeatureVirtualization,
FeatureCrypto,
FeatureCRC]>;
[ARM] Add ARMv8.2-A to TargetParser Add ARMv8.2-A to TargetParser, so that it can be used by the clang command-line options and the .arch directive. Most testing of this will be done in clang, checking that the command-line options that this enables work. Differential Revision: http://reviews.llvm.org/D15037 llvm-svn: 254400
2015-12-01 18:33:56 +08:00
def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
FeatureAClass,
FeatureDB,
FeatureFPARMv8,
FeatureNEON,
FeatureDSP,
FeatureTrustZone,
FeatureMP,
FeatureVirtualization,
FeatureCrypto,
FeatureCRC]>;
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
// Aliases
def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
//===----------------------------------------------------------------------===//
// ARM processors
//
// Dummy CPU, used to target architectures
def : ProcNoItin<"generic", []>;
def : ProcNoItin<"arm8", [ARMv4]>;
def : ProcNoItin<"arm810", [ARMv4]>;
def : ProcNoItin<"strongarm", [ARMv4]>;
def : ProcNoItin<"strongarm110", [ARMv4]>;
def : ProcNoItin<"strongarm1100", [ARMv4]>;
def : ProcNoItin<"strongarm1110", [ARMv4]>;
def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
def : ProcNoItin<"arm710t", [ARMv4t]>;
def : ProcNoItin<"arm720t", [ARMv4t]>;
def : ProcNoItin<"arm9", [ARMv4t]>;
def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
def : ProcNoItin<"arm920", [ARMv4t]>;
def : ProcNoItin<"arm920t", [ARMv4t]>;
def : ProcNoItin<"arm922t", [ARMv4t]>;
def : ProcNoItin<"arm940t", [ARMv4t]>;
def : ProcNoItin<"ep9312", [ARMv4t]>;
def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
def : ProcNoItin<"arm1020t", [ARMv5t]>;
def : ProcNoItin<"arm9e", [ARMv5te]>;
def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
def : ProcNoItin<"arm946e-s", [ARMv5te]>;
def : ProcNoItin<"arm966e-s", [ARMv5te]>;
def : ProcNoItin<"arm968e-s", [ARMv5te]>;
def : ProcNoItin<"arm10e", [ARMv5te]>;
def : ProcNoItin<"arm1020e", [ARMv5te]>;
def : ProcNoItin<"arm1022e", [ARMv5te]>;
def : ProcNoItin<"xscale", [ARMv5te]>;
def : ProcNoItin<"iwmmxt", [ARMv5te]>;
def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
FeatureVFP2,
FeatureHasSlowFPVMLx]>;
def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
Handle ARMv6KZ naming Summary: * ARMv6KZ is the "canonical" name, given in the ARMARM * ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM * ARMv6ZK is a popular misspelling, which we should support as an alias. The patch corrects the handling of the names. Functional changes: * ARMv6Z no longer treated as an architecture in its own right * ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias * arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K * default ARMv6K CPU changed to arm1176j-s Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14568 llvm-svn: 253206
2015-11-16 22:05:32 +08:00
def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
FeatureVFP2,
FeatureHasSlowFPVMLx]>;
def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
FeatureVFP2,
FeatureHasSlowFPVMLx]>;
def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
FeatureVFP2,
FeatureHasSlowFPVMLx]>;
Add placeholder for thumb2 stuff llvm-svn: 72593
2009-05-30 07:41:08 +08:00
Add cortex-a5 subtarget to the supported ARM architectures llvm-svn: 168933
2012-11-30 03:48:01 +08:00
// FIXME: A5 has currently the same Schedule model as A8
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
FeatureHasRAS,
FeatureTrustZone,
FeatureSlowFPBrcc,
FeatureHasSlowFPVMLx,
FeatureVMLxForwarding,
FeatureT2XtPk,
FeatureMP,
FeatureVFP4]>;
def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
FeatureHasRAS,
FeatureTrustZone,
FeatureSlowFPBrcc,
FeatureHasSlowFPVMLx,
FeatureVMLxForwarding,
FeatureT2XtPk,
FeatureMP,
FeatureVFP4,
FeatureHWDiv,
FeatureHWDivARM,
FeatureVirtualization]>;
def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
FeatureHasRAS,
FeatureTrustZone,
FeatureSlowFPBrcc,
FeatureHasSlowFPVMLx,
FeatureVMLxForwarding,
FeatureT2XtPk]>;
def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
FeatureHasRAS,
FeatureTrustZone,
FeatureVMLxForwarding,
FeatureT2XtPk,
FeatureFP16,
FeatureAvoidPartialCPSR,
FeatureMP]>;
Add support for Cortex-A12. Patch by Oliver Stannard! llvm-svn: 195448
2013-11-22 19:53:16 +08:00
// FIXME: A12 has currently the same Schedule model as A9
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
FeatureHasRAS,
FeatureTrustZone,
FeatureVMLxForwarding,
FeatureT2XtPk,
FeatureVFP4,
FeatureHWDiv,
FeatureHWDivARM,
FeatureAvoidPartialCPSR,
FeatureVirtualization,
FeatureMP]>;
// FIXME: A15 has currently the same Schedule model as A9.
def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
FeatureHasRAS,
FeatureTrustZone,
FeatureT2XtPk,
FeatureVFP4,
FeatureMP,
FeatureHWDiv,
FeatureHWDivARM,
FeatureAvoidPartialCPSR,
FeatureVirtualization]>;
Add support for Cortex-A12. Patch by Oliver Stannard! llvm-svn: 195448
2013-11-22 19:53:16 +08:00
Adds support for the Cortex-A17 to the ARM backend Patch by Matthew Wahab. llvm-svn: 219606
2014-10-13 18:22:19 +08:00
// FIXME: A17 has currently the same Schedule model as A9
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
FeatureHasRAS,
FeatureTrustZone,
FeatureMP,
FeatureVMLxForwarding,
FeatureT2XtPk,
FeatureVFP4,
FeatureHWDiv,
FeatureHWDivARM,
FeatureAvoidPartialCPSR,
FeatureVirtualization]>;
Adds support for the Cortex-A17 to the ARM backend Patch by Matthew Wahab. llvm-svn: 219606
2014-10-13 18:22:19 +08:00
ARM: add cyclone CPU with ZeroCycleZeroing feature. The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
2014-04-01 21:22:02 +08:00
// FIXME: krait has currently the same Schedule model as A9
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
// FIXME: krait has currently the same features as A9 plus VFP4 and hardware
// division features.
def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
FeatureHasRAS,
FeatureVMLxForwarding,
FeatureT2XtPk,
FeatureFP16,
FeatureAvoidPartialCPSR,
FeatureVFP4,
FeatureHWDiv,
FeatureHWDivARM]>;
def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
FeatureHasRAS,
FeatureNEONForFP,
FeatureT2XtPk,
FeatureVFP4,
FeatureMP,
FeatureHWDiv,
FeatureHWDivARM,
FeatureAvoidPartialCPSR,
FeatureAvoidMOVsShOp,
FeatureHasSlowFPVMLx]>;
ARM: add cyclone CPU with ZeroCycleZeroing feature. The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
2014-04-01 21:22:02 +08:00
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
// FIXME: R4 has currently the same ProcessorModel as A8.
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
FeatureHasRAS,
FeatureAvoidPartialCPSR,
FeatureT2XtPk]>;
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
// FIXME: R4F has currently the same ProcessorModel as A8.
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
FeatureHasRAS,
FeatureSlowFPBrcc,
FeatureHasSlowFPVMLx,
FeatureVFP3,
FeatureD16,
FeatureAvoidPartialCPSR,
FeatureT2XtPk]>;
[ARM] support for Cortex-R4/R4F Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
2015-04-09 22:07:28 +08:00
Add ARM cortex-r5 subtarget. llvm-svn: 170840
2012-12-21 12:35:05 +08:00
// FIXME: R5 has currently the same ProcessorModel as A8.
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
FeatureHasRAS,
FeatureVFP3,
FeatureD16,
FeatureSlowFPBrcc,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
FeatureAvoidPartialCPSR,
FeatureT2XtPk]>;
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786
2010-08-11 14:30:38 +08:00
[ARM] Add missing M/R class CPUs Add some of the missing M and R class Cortex CPUs, namely: Cortex-M0+ (called Cortex-M0plus for GCC compatibility) Cortex-M1 SC000 SC300 Cortex-R5 llvm-svn: 229660
2015-02-18 18:33:30 +08:00
// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
FeatureHasRAS,
FeatureVFP3,
FeatureVFPOnlySP,
FeatureD16,
[ARM] Flag vcvt{t,b} with an f16 type specifier as part of the FP16 extension Additionally correct the Cortex-R7 definition to allow the FP16 feature. llvm-svn: 254900
2015-12-07 18:54:36 +08:00
FeatureFP16,
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
FeatureMP,
FeatureSlowFPBrcc,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
FeatureAvoidPartialCPSR,
FeatureT2XtPk]>;
def : ProcNoItin<"cortex-m3", [ARMv7m]>;
def : ProcNoItin<"sc300", [ARMv7m]>;
def : ProcNoItin<"cortex-m4", [ARMv7em,
FeatureVFP4,
FeatureVFPOnlySP,
FeatureD16]>;
def : ProcNoItin<"cortex-m7", [ARMv7em,
FeatureFPARMv8,
FeatureD16]>;
[AArch64]: Add support for Cortex-A35 Adds support for the new Cortex-A35 ARMv8-A core. llvm-svn: 254503
2015-12-02 19:53:44 +08:00
def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
FeatureHWDiv,
FeatureHWDivARM,
FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
FeatureHWDiv,
FeatureHWDivARM,
FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
FeatureHWDiv,
FeatureHWDivARM,
FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
FeatureHWDiv,
FeatureHWDivARM,
FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
Add a subtarget feature 'v8' to the ARM backend. This allows for targeting the ARMv8 AArch32 variant. llvm-svn: 184967
2013-06-27 00:58:26 +08:00
ARM: add cyclone CPU with ZeroCycleZeroing feature. The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
2014-04-01 21:22:02 +08:00
// Cyclone is very similar to swift
[ARM] Introduce subtarget features per ARM architecture. This allows for accurate architecture targeting as well as removing duplicate information (hardcoded feature strings) from MCTargetDesc. llvm-svn: 253196
2015-11-16 19:10:19 +08:00
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
FeatureHasRAS,
FeatureNEONForFP,
FeatureT2XtPk,
FeatureVFP4,
FeatureMP,
FeatureHWDiv,
FeatureHWDivARM,
FeatureAvoidPartialCPSR,
FeatureAvoidMOVsShOp,
FeatureHasSlowFPVMLx,
FeatureCrypto,
FeatureZCZeroing]>;
[AArch64] Add support for Samsung Exynos-M1 Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15663 llvm-svn: 256828
2016-01-05 20:51:59 +08:00
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
FeatureHWDiv,
FeatureHWDivARM,
FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;
Added support for mcpu krait - krait processor currently modeled with the same features as A9. - Krait processor additionally has VFP4 (fused multiply add/sub) and hardware division features enabled. - krait has currently the same Schedule model as A9 - krait cpu flag is not recognized by the GNU assembler yet, it is replaced with march=armv7-a to avoid a lower march from being used. llvm-svn: 196619
2013-12-07 06:48:17 +08:00
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 06:18:28 +08:00
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "ARMRegisterInfo.td"
Use CallConvLower.h and TableGen descriptions of the calling conventions for ARM. Patch by Sandeep Patel. llvm-svn: 69371
2009-04-18 03:07:39 +08:00
include "ARMCallingConv.td"
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 06:18:28 +08:00
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "ARMInstrInfo.td"
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
2010-04-05 11:10:20 +08:00
def ARMInstrInfo : InstrInfo;
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 06:18:28 +08:00
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
def ARMAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
int PassSubtarget = 1;
int Variant = 0;
bit isMCAsmWriter = 1;
}
[AsmParser] Backends can parameterize ASM tokenization. llvm-svn: 252439
2015-11-09 08:31:07 +08:00
def ARMAsmParserVariant : AsmParserVariant {
int Variant = 0;
string Name = "ARM";
string BreakCharacters = ".";
}
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 06:18:28 +08:00
def ARM : Target {
// Pull in Instruction Info:
let InstructionSet = ARMInstrInfo;
[ARM] Enable changing instprinter's behavior based on the per-function subtarget. llvm-svn: 233451
2015-03-28 07:41:42 +08:00
let AssemblyWriters = [ARMAsmWriter];
[AsmParser] Backends can parameterize ASM tokenization. llvm-svn: 252439
2015-11-09 08:31:07 +08:00
let AssemblyParserVariants = [ARMAsmParserVariant];
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 06:18:28 +08:00
}