2006-05-15 06:18:28 +08:00
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//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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2006-05-15 06:18:28 +08:00
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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2017-11-17 09:07:10 +08:00
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#include "ARMTargetMachine.h"
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2006-05-15 06:18:28 +08:00
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#include "ARM.h"
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2017-06-22 17:39:36 +08:00
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#include "ARMMacroFusion.h"
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2017-11-17 09:07:10 +08:00
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#include "ARMSubtarget.h"
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2014-11-13 17:26:31 +08:00
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#include "ARMTargetObjectFile.h"
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2015-01-31 19:17:59 +08:00
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#include "ARMTargetTransformInfo.h"
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2017-01-31 08:56:17 +08:00
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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2018-01-22 18:06:33 +08:00
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#include "llvm/CodeGen/ExecutionDomainFix.h"
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2017-01-31 08:56:17 +08:00
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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2016-11-11 16:27:37 +08:00
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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2017-01-31 08:56:17 +08:00
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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2016-11-11 16:27:37 +08:00
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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2017-01-31 08:56:17 +08:00
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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2016-11-11 16:27:37 +08:00
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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2017-01-31 08:56:17 +08:00
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2017-06-09 22:07:21 +08:00
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#include "llvm/CodeGen/MachineScheduler.h"
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2007-05-16 10:01:49 +08:00
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#include "llvm/CodeGen/Passes.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetLoweringObjectFile.h"
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2016-05-10 11:21:59 +08:00
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#include "llvm/CodeGen/TargetPassConfig.h"
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2017-01-31 08:56:17 +08:00
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/DataLayout.h"
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2014-10-06 14:45:36 +08:00
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#include "llvm/IR/Function.h"
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2017-01-31 08:56:17 +08:00
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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2010-12-06 06:04:16 +08:00
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#include "llvm/Support/CommandLine.h"
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2017-01-31 08:56:17 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2016-08-17 10:08:28 +08:00
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#include "llvm/Support/TargetParser.h"
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2016-11-11 16:27:37 +08:00
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#include "llvm/Support/TargetRegistry.h"
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2007-01-19 15:51:42 +08:00
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#include "llvm/Target/TargetOptions.h"
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2011-10-18 01:17:43 +08:00
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#include "llvm/Transforms/Scalar.h"
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2017-01-31 08:56:17 +08:00
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#include <cassert>
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#include <memory>
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#include <string>
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2006-05-15 06:18:28 +08:00
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using namespace llvm;
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2013-03-16 02:28:25 +08:00
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static cl::opt<bool>
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DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
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cl::desc("Inhibit optimization of S->D register accesses on A15"),
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cl::init(false));
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2014-05-30 18:09:59 +08:00
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static cl::opt<bool>
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EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
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cl::desc("Run SimplifyCFG after expanding atomic operations"
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" to make use of cmpxchg flow-based information"),
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cl::init(true));
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2015-03-27 02:38:04 +08:00
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static cl::opt<bool>
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EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
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cl::desc("Enable ARM load/store optimization pass"),
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cl::init(true));
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2015-04-11 08:06:36 +08:00
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// FIXME: Unify control over GlobalMerge.
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static cl::opt<cl::boolOrDefault>
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EnableGlobalMerge("arm-global-merge", cl::Hidden,
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cl::desc("Enable the global merge pass"));
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2017-03-18 13:08:58 +08:00
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namespace llvm {
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2018-01-22 18:05:23 +08:00
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void initializeARMExecutionDomainFixPass(PassRegistry&);
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2017-03-18 13:08:58 +08:00
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}
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2009-08-11 23:33:49 +08:00
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extern "C" void LLVMInitializeARMTarget() {
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2009-07-25 14:49:55 +08:00
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// Register the target.
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2016-10-10 07:00:34 +08:00
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RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
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2017-05-24 18:18:57 +08:00
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RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
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2016-10-10 07:00:34 +08:00
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RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
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2017-05-24 18:18:57 +08:00
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RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
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2016-07-16 10:24:10 +08:00
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PassRegistry &Registry = *PassRegistry::getPassRegistry();
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2016-11-11 16:27:37 +08:00
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initializeGlobalISel(Registry);
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2016-07-16 10:24:10 +08:00
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initializeARMLoadStoreOptPass(Registry);
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initializeARMPreAllocLoadStoreOptPass(Registry);
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2017-02-13 22:07:25 +08:00
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initializeARMConstantIslandsPass(Registry);
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2018-01-22 18:05:23 +08:00
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initializeARMExecutionDomainFixPass(Registry);
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2017-09-06 06:45:23 +08:00
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initializeARMExpandPseudoPass(Registry);
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2017-12-19 20:19:08 +08:00
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initializeThumb2SizeReducePass(Registry);
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2009-07-25 14:49:55 +08:00
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}
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2009-06-17 04:12:29 +08:00
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2014-11-13 17:26:31 +08:00
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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if (TT.isOSBinFormatMachO())
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2017-01-31 08:56:17 +08:00
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return llvm::make_unique<TargetLoweringObjectFileMachO>();
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2014-11-13 17:26:31 +08:00
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if (TT.isOSWindows())
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2017-01-31 08:56:17 +08:00
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return llvm::make_unique<TargetLoweringObjectFileCOFF>();
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return llvm::make_unique<ARMElfTargetObjectFile>();
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2014-11-13 17:26:31 +08:00
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}
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2014-12-18 10:20:58 +08:00
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static ARMBaseTargetMachine::ARMABI
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computeTargetABI(const Triple &TT, StringRef CPU,
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const TargetOptions &Options) {
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2017-06-30 08:03:54 +08:00
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StringRef ABIName = Options.MCOptions.getABIName();
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if (ABIName.empty())
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ABIName = ARM::computeDefaultTargetABI(TT, CPU);
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if (ABIName == "aapcs16")
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2015-10-29 06:46:43 +08:00
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return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
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2017-06-30 08:03:54 +08:00
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else if (ABIName.startswith("aapcs"))
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2014-12-18 10:20:58 +08:00
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return ARMBaseTargetMachine::ARM_ABI_AAPCS;
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2017-06-30 08:03:54 +08:00
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else if (ABIName.startswith("apcs"))
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2014-12-18 10:20:58 +08:00
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return ARMBaseTargetMachine::ARM_ABI_APCS;
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2017-06-30 08:03:54 +08:00
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llvm_unreachable("Unhandled/unknown ABI Name!");
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return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
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2014-12-18 10:20:58 +08:00
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}
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2015-06-11 23:34:59 +08:00
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static std::string computeDataLayout(const Triple &TT, StringRef CPU,
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2015-03-12 08:07:24 +08:00
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const TargetOptions &Options,
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2015-01-27 03:03:15 +08:00
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bool isLittle) {
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2015-06-11 23:34:59 +08:00
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auto ABI = computeTargetABI(TT, CPU, Options);
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2017-01-31 08:56:17 +08:00
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std::string Ret;
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2015-01-27 03:03:15 +08:00
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if (isLittle)
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// Little endian.
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Ret += "e";
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else
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// Big endian.
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Ret += "E";
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2015-06-11 23:34:59 +08:00
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Ret += DataLayout::getManglingComponent(TT);
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2015-01-27 03:03:15 +08:00
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// Pointers are 32 bits and aligned to 32 bits.
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Ret += "-p:32:32";
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// ABIs other than APCS have 64 bit integers with natural alignment.
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if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
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Ret += "-i64:64";
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// We have 64 bits floats. The APCS ABI requires them to be aligned to 32
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// bits, others to 64 bits. We always try to align to 64 bits.
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if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
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Ret += "-f64:32:64";
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// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
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// to 64. We always ty to give them natural alignment.
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if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
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Ret += "-v64:32:64-v128:32:128";
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2015-10-29 06:46:43 +08:00
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else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
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2015-01-27 03:03:15 +08:00
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Ret += "-v128:64:128";
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// Try to align aggregates to 32 bits (the default is 64 bits, which has no
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// particular hardware support on 32-bit ARM).
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Ret += "-a:0:32";
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// Integer registers are 32 bits.
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Ret += "-n32";
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// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
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// aligned everywhere else.
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2015-10-29 06:46:43 +08:00
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if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
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2015-01-27 03:03:15 +08:00
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Ret += "-S128";
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else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
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Ret += "-S64";
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else
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Ret += "-S32";
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return Ret;
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}
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2016-05-19 06:04:49 +08:00
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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2016-05-28 18:41:15 +08:00
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// Default relocation model on Darwin is PIC.
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return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
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2016-05-28 12:47:13 +08:00
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2016-08-08 23:28:31 +08:00
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if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
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assert(TT.isOSBinFormatELF() &&
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"ROPI/RWPI currently only supported for ELF");
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2016-05-28 12:47:13 +08:00
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// DynamicNoPIC is only used on darwin.
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if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
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return Reloc::Static;
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2016-05-19 06:04:49 +08:00
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return *RM;
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}
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2017-08-03 10:16:21 +08:00
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static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
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if (CM)
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return *CM;
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return CodeModel::Small;
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}
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2016-05-19 00:00:24 +08:00
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/// Create an ARM architecture model.
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2007-02-23 11:14:31 +08:00
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///
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2015-06-12 03:41:26 +08:00
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ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
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2011-07-19 14:37:02 +08:00
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StringRef CPU, StringRef FS,
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2011-12-03 06:16:29 +08:00
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const TargetOptions &Options,
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2016-05-19 06:04:49 +08:00
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Optional<Reloc::Model> RM,
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2017-08-03 10:16:21 +08:00
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Optional<CodeModel::Model> CM,
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2014-06-27 03:30:02 +08:00
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CodeGenOpt::Level OL, bool isLittle)
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2017-10-13 06:57:28 +08:00
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: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
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CPU, FS, Options, getEffectiveRelocModel(TT, RM),
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getEffectiveCodeModel(CM), OL),
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2015-06-12 03:41:26 +08:00
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TargetABI(computeTargetABI(TT, CPU, Options)),
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2017-07-01 11:41:53 +08:00
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TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
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2013-12-18 22:18:36 +08:00
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// Default to triple-appropriate float ABI
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2017-07-01 11:41:53 +08:00
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if (Options.FloatABIType == FloatABI::Default) {
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if (TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
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TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
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TargetTriple.getEnvironment() == Triple::EABIHF ||
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TargetTriple.isOSWindows() ||
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TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
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this->Options.FloatABIType = FloatABI::Hard;
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else
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this->Options.FloatABIType = FloatABI::Soft;
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}
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2015-11-09 20:40:30 +08:00
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// Default to triple-appropriate EABI
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if (Options.EABIVersion == EABI::Default ||
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Options.EABIVersion == EABI::Unknown) {
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2016-06-25 05:14:33 +08:00
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// musl is compatible with glibc with regard to EABI version
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2017-07-01 11:41:53 +08:00
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if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
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2017-08-28 14:47:47 +08:00
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TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
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TargetTriple.getEnvironment() == Triple::MuslEABI ||
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TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
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!(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
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2015-11-09 20:40:30 +08:00
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this->Options.EABIVersion = EABI::GNU;
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else
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this->Options.EABIVersion = EABI::EABI5;
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}
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2017-05-24 18:18:57 +08:00
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initAsmInfo();
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2008-10-31 00:10:54 +08:00
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}
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2006-05-15 06:18:28 +08:00
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2017-01-31 08:56:17 +08:00
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ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
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2014-11-21 07:37:18 +08:00
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2014-10-06 14:45:36 +08:00
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const ARMSubtarget *
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ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
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2015-02-14 10:24:44 +08:00
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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2014-10-06 14:45:36 +08:00
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function before we can generate a subtarget. We also need to use
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// it as a key for the subtarget since that can be the only difference
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// between two functions.
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2015-05-12 09:26:05 +08:00
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bool SoftFloat =
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F.getFnAttribute("use-soft-float").getValueAsString() == "true";
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// If the soft float attribute is set on the function turn on the soft float
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// subtarget feature.
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if (SoftFloat)
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FS += FS.empty() ? "+soft-float" : ",+soft-float";
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|
|
auto &I = SubtargetMap[CPU + FS];
|
2014-10-06 14:45:36 +08:00
|
|
|
if (!I) {
|
|
|
|
// This needs to be done before we create a new subtarget since any
|
|
|
|
// creation will depend on the TM and the code generation flags on the
|
|
|
|
// function that reside in TargetOptions.
|
|
|
|
resetTargetOptions(F);
|
2015-06-16 23:44:21 +08:00
|
|
|
I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
|
[ARM] Emit error when ARM exec mode is not available.
Summary:
A similar error message has been removed from the ARMTargetMachineBase
constructor in r306939. With this patch, we generate an error message
for the example below, compiled with -mcpu=cortex-m0, which does not
have ARM execution mode.
__attribute__((target("arm"))) int foo(int a, int b)
{
return a + b % a;
}
__attribute__((target("thumb"))) int bar(int a, int b)
{
return a + b % a;
}
By adding this error message to ARMBaseTargetMachine::getSubtargetImpl,
we can deal with functions that set -thumb-mode in target-features.
At the moment it seems like Clang does not have access to target-feature
specific information, so adding the error message to the frontend will
be harder.
Reviewers: echristo, richard.barton.arm, t.p.northover, rengolin, efriedma
Reviewed By: echristo, efriedma
Subscribers: efriedma, aemerson, javed.absar, kristof.beyls
Differential Revision: https://reviews.llvm.org/D35627
llvm-svn: 310486
2017-08-09 23:39:10 +08:00
|
|
|
|
|
|
|
if (!I->isThumb() && !I->hasARMOps())
|
|
|
|
F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
|
|
|
|
"instructions, but the target does not support ARM mode execution.");
|
2016-11-15 23:38:15 +08:00
|
|
|
}
|
[ARM] Emit error when ARM exec mode is not available.
Summary:
A similar error message has been removed from the ARMTargetMachineBase
constructor in r306939. With this patch, we generate an error message
for the example below, compiled with -mcpu=cortex-m0, which does not
have ARM execution mode.
__attribute__((target("arm"))) int foo(int a, int b)
{
return a + b % a;
}
__attribute__((target("thumb"))) int bar(int a, int b)
{
return a + b % a;
}
By adding this error message to ARMBaseTargetMachine::getSubtargetImpl,
we can deal with functions that set -thumb-mode in target-features.
At the moment it seems like Clang does not have access to target-feature
specific information, so adding the error message to the frontend will
be harder.
Reviewers: echristo, richard.barton.arm, t.p.northover, rengolin, efriedma
Reviewed By: echristo, efriedma
Subscribers: efriedma, aemerson, javed.absar, kristof.beyls
Differential Revision: https://reviews.llvm.org/D35627
llvm-svn: 310486
2017-08-09 23:39:10 +08:00
|
|
|
|
2014-10-06 14:45:36 +08:00
|
|
|
return I.get();
|
|
|
|
}
|
|
|
|
|
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
Re-land r321234. It had to be reverted because it broke the shared
library build. The shared library build broke because there was a
missing LLVMBuild dependency from lib/Passes (which calls
TargetMachine::getTargetIRAnalysis) to lib/Target. As far as I can
tell, this problem was always there but was somehow masked
before (perhaps because TargetMachine::getTargetIRAnalysis was a
virtual function).
Original commit message:
This makes the TargetMachine interface a bit simpler. We still need
the std::function in TargetIRAnalysis to avoid having to add a
dependency from Analysis to Target.
See discussion:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html
I avoided adding all of the backend owners to this review since the
change is simple, but let me know if you feel differently about this.
Reviewers: echristo, MatzeB, hfinkel
Reviewed By: hfinkel
Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D41464
llvm-svn: 321375
2017-12-23 02:21:59 +08:00
|
|
|
TargetTransformInfo
|
|
|
|
ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
|
|
|
|
return TargetTransformInfo(ARMTTIImpl(this, F));
|
Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
llvm-svn: 171681
2013-01-07 09:37:14 +08:00
|
|
|
}
|
|
|
|
|
2015-06-12 03:41:26 +08:00
|
|
|
ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
|
2014-06-27 03:30:02 +08:00
|
|
|
StringRef CPU, StringRef FS,
|
|
|
|
const TargetOptions &Options,
|
2016-05-19 06:04:49 +08:00
|
|
|
Optional<Reloc::Model> RM,
|
2017-08-03 10:16:21 +08:00
|
|
|
Optional<CodeModel::Model> CM,
|
|
|
|
CodeGenOpt::Level OL, bool JIT)
|
2017-05-24 18:18:57 +08:00
|
|
|
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
2014-03-28 22:35:30 +08:00
|
|
|
|
2015-06-12 03:41:26 +08:00
|
|
|
ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
|
2014-06-27 03:30:02 +08:00
|
|
|
StringRef CPU, StringRef FS,
|
|
|
|
const TargetOptions &Options,
|
2016-05-19 06:04:49 +08:00
|
|
|
Optional<Reloc::Model> RM,
|
2017-08-03 10:16:21 +08:00
|
|
|
Optional<CodeModel::Model> CM,
|
|
|
|
CodeGenOpt::Level OL, bool JIT)
|
2017-05-24 18:18:57 +08:00
|
|
|
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
|
2014-03-28 22:35:30 +08:00
|
|
|
|
2012-02-03 13:12:41 +08:00
|
|
|
namespace {
|
2017-01-31 08:56:17 +08:00
|
|
|
|
2012-02-03 13:12:41 +08:00
|
|
|
/// ARM Code Generator Pass Configuration Options.
|
|
|
|
class ARMPassConfig : public TargetPassConfig {
|
|
|
|
public:
|
2017-05-31 05:36:41 +08:00
|
|
|
ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
|
2017-10-20 22:29:17 +08:00
|
|
|
: TargetPassConfig(TM, PM) {
|
|
|
|
if (TM.getOptLevel() != CodeGenOpt::None) {
|
|
|
|
ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
|
|
|
|
TM.getTargetFeatureString());
|
|
|
|
if (STI.hasFeature(ARM::FeatureUseMISched))
|
|
|
|
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
|
|
|
|
}
|
|
|
|
}
|
2012-02-03 13:12:41 +08:00
|
|
|
|
|
|
|
ARMBaseTargetMachine &getARMTargetMachine() const {
|
|
|
|
return getTM<ARMBaseTargetMachine>();
|
|
|
|
}
|
|
|
|
|
2017-06-09 22:07:21 +08:00
|
|
|
ScheduleDAGInstrs *
|
|
|
|
createMachineScheduler(MachineSchedContext *C) const override {
|
|
|
|
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
|
|
|
|
// add DAG Mutations here.
|
2017-06-22 17:39:36 +08:00
|
|
|
const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
|
|
|
|
if (ST.hasFusion())
|
|
|
|
DAG->addMutation(createARMMacroFusionDAGMutation());
|
2017-06-09 22:07:21 +08:00
|
|
|
return DAG;
|
|
|
|
}
|
|
|
|
|
|
|
|
ScheduleDAGInstrs *
|
|
|
|
createPostMachineScheduler(MachineSchedContext *C) const override {
|
|
|
|
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
|
|
|
|
// add DAG Mutations here.
|
2017-06-22 17:39:36 +08:00
|
|
|
const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
|
|
|
|
if (ST.hasFusion())
|
|
|
|
DAG->addMutation(createARMMacroFusionDAGMutation());
|
2017-06-09 22:07:21 +08:00
|
|
|
return DAG;
|
|
|
|
}
|
|
|
|
|
2014-05-30 18:09:59 +08:00
|
|
|
void addIRPasses() override;
|
2014-03-10 10:09:33 +08:00
|
|
|
bool addPreISel() override;
|
|
|
|
bool addInstSelector() override;
|
2016-11-11 16:27:37 +08:00
|
|
|
bool addIRTranslator() override;
|
|
|
|
bool addLegalizeMachineIR() override;
|
|
|
|
bool addRegBankSelect() override;
|
|
|
|
bool addGlobalInstructionSelect() override;
|
2014-12-12 05:26:47 +08:00
|
|
|
void addPreRegAlloc() override;
|
|
|
|
void addPreSched2() override;
|
|
|
|
void addPreEmitPass() override;
|
2012-02-03 13:12:41 +08:00
|
|
|
};
|
2017-01-31 08:56:17 +08:00
|
|
|
|
2018-01-22 18:05:23 +08:00
|
|
|
class ARMExecutionDomainFix : public ExecutionDomainFix {
|
2017-03-18 13:08:58 +08:00
|
|
|
public:
|
|
|
|
static char ID;
|
2018-01-22 18:05:23 +08:00
|
|
|
ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
|
2017-03-18 13:08:58 +08:00
|
|
|
StringRef getPassName() const override {
|
2018-01-22 18:05:23 +08:00
|
|
|
return "ARM Execution Domain Fix";
|
2017-03-18 13:08:58 +08:00
|
|
|
}
|
|
|
|
};
|
2018-01-22 18:05:23 +08:00
|
|
|
char ARMExecutionDomainFix::ID;
|
2017-03-18 13:08:58 +08:00
|
|
|
|
2017-01-31 08:56:17 +08:00
|
|
|
} // end anonymous namespace
|
2012-02-03 13:12:41 +08:00
|
|
|
|
2018-01-22 18:05:23 +08:00
|
|
|
INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
|
|
|
|
"ARM Execution Domain Fix", false, false)
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
|
|
|
|
INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
|
|
|
|
"ARM Execution Domain Fix", false, false)
|
2017-03-18 13:08:58 +08:00
|
|
|
|
2012-02-04 10:56:59 +08:00
|
|
|
TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
|
2017-05-31 05:36:41 +08:00
|
|
|
return new ARMPassConfig(*this, PM);
|
2012-02-03 13:12:41 +08:00
|
|
|
}
|
|
|
|
|
2014-05-30 18:09:59 +08:00
|
|
|
void ARMPassConfig::addIRPasses() {
|
2014-08-21 22:35:47 +08:00
|
|
|
if (TM->Options.ThreadModel == ThreadModel::Single)
|
|
|
|
addPass(createLowerAtomicPass());
|
|
|
|
else
|
2017-05-19 01:21:13 +08:00
|
|
|
addPass(createAtomicExpandPass());
|
2014-04-03 19:44:58 +08:00
|
|
|
|
2014-06-20 05:03:04 +08:00
|
|
|
// Cmpxchg instructions are often used with a subsequent comparison to
|
|
|
|
// determine whether it succeeded. We can exploit existing control-flow in
|
|
|
|
// ldrex/strex loops to simplify this, but it needs tidying up.
|
2015-06-09 02:50:43 +08:00
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
|
2017-10-29 02:43:07 +08:00
|
|
|
addPass(createCFGSimplificationPass(
|
2017-12-15 06:05:20 +08:00
|
|
|
1, false, false, true, true, [this](const Function &F) {
|
2017-10-29 02:43:07 +08:00
|
|
|
const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
|
|
|
|
return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
|
|
|
|
}));
|
2014-05-30 18:09:59 +08:00
|
|
|
|
|
|
|
TargetPassConfig::addIRPasses();
|
[ARM] Lower interleaved memory accesses to vldN/vstN intrinsics.
This patch also adds a function to calculate the cost of interleaved memory accesses.
E.g. Lower an interleaved load:
%wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
%v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
%v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
into:
%vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4)
%vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0
%vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1
E.g. Lower an interleaved store:
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4
into:
%sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
%sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
%sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)
Differential Revision: http://reviews.llvm.org/D10533
llvm-svn: 240755
2015-06-26 10:45:36 +08:00
|
|
|
|
|
|
|
// Match interleaved memory accesses to ldN/stN intrinsics.
|
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None)
|
2017-05-19 01:21:13 +08:00
|
|
|
addPass(createInterleavedAccessPass());
|
2014-05-30 18:09:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMPassConfig::addPreISel() {
|
2015-06-05 04:39:23 +08:00
|
|
|
if ((TM->getOptLevel() != CodeGenOpt::None &&
|
2015-04-11 08:06:36 +08:00
|
|
|
EnableGlobalMerge == cl::BOU_UNSET) ||
|
2015-06-05 04:39:23 +08:00
|
|
|
EnableGlobalMerge == cl::BOU_TRUE) {
|
2015-02-24 03:28:45 +08:00
|
|
|
// FIXME: This is using the thumb1 only constant value for
|
|
|
|
// maximal global offset for merging globals. We may want
|
|
|
|
// to look into using the old value for non-thumb1 code of
|
|
|
|
// 4095 based on the TargetMachine, but this starts to become
|
|
|
|
// tricky when doing code gen per function.
|
2015-06-05 04:39:23 +08:00
|
|
|
bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
|
|
|
|
(EnableGlobalMerge == cl::BOU_UNSET);
|
2015-08-03 20:13:33 +08:00
|
|
|
// Merging of extern globals is enabled by default on non-Mach-O as we
|
|
|
|
// expect it to be generally either beneficial or harmless. On Mach-O it
|
|
|
|
// is disabled as we emit the .subsections_via_symbols directive which
|
|
|
|
// means that merging extern globals is not safe.
|
|
|
|
bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
|
|
|
|
addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
|
|
|
|
MergeExternalByDefault));
|
2015-06-05 04:39:23 +08:00
|
|
|
}
|
2006-05-15 06:18:28 +08:00
|
|
|
|
2010-07-25 05:52:08 +08:00
|
|
|
return false;
|
|
|
|
}
|
2007-01-19 15:51:42 +08:00
|
|
|
|
2012-02-03 13:12:41 +08:00
|
|
|
bool ARMPassConfig::addInstSelector() {
|
2012-07-03 03:48:31 +08:00
|
|
|
addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
|
2006-09-04 12:14:57 +08:00
|
|
|
return false;
|
|
|
|
}
|
2006-09-19 23:49:25 +08:00
|
|
|
|
2016-11-11 16:27:37 +08:00
|
|
|
bool ARMPassConfig::addIRTranslator() {
|
|
|
|
addPass(new IRTranslator());
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMPassConfig::addLegalizeMachineIR() {
|
|
|
|
addPass(new Legalizer());
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMPassConfig::addRegBankSelect() {
|
|
|
|
addPass(new RegBankSelect());
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMPassConfig::addGlobalInstructionSelect() {
|
|
|
|
addPass(new InstructionSelect());
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-12-12 05:26:47 +08:00
|
|
|
void ARMPassConfig::addPreRegAlloc() {
|
2015-03-27 02:38:04 +08:00
|
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
2014-12-12 07:18:03 +08:00
|
|
|
addPass(createMLxExpansionPass());
|
2015-03-27 02:38:04 +08:00
|
|
|
|
|
|
|
if (EnableARMLoadStoreOpt)
|
|
|
|
addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
|
|
|
|
|
|
|
|
if (!DisableA15SDOptimization)
|
|
|
|
addPass(createA15SDOptimizerPass());
|
2013-03-16 02:28:25 +08:00
|
|
|
}
|
2009-06-13 17:12:55 +08:00
|
|
|
}
|
|
|
|
|
2014-12-12 05:26:47 +08:00
|
|
|
void ARMPassConfig::addPreSched2() {
|
2011-11-16 16:38:26 +08:00
|
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
2015-03-27 02:38:04 +08:00
|
|
|
if (EnableARMLoadStoreOpt)
|
|
|
|
addPass(createARMLoadStoreOptimizationPass());
|
|
|
|
|
2018-01-22 18:05:23 +08:00
|
|
|
addPass(new ARMExecutionDomainFix());
|
2018-01-22 18:06:50 +08:00
|
|
|
addPass(createBreakFalseDeps());
|
2010-11-12 04:50:14 +08:00
|
|
|
}
|
2009-09-30 16:53:01 +08:00
|
|
|
|
2009-11-07 07:52:48 +08:00
|
|
|
// Expand some pseudo instructions into multiple instructions to allow
|
|
|
|
// proper scheduling.
|
2014-12-12 07:18:03 +08:00
|
|
|
addPass(createARMExpandPseudoPass());
|
2009-11-07 07:52:48 +08:00
|
|
|
|
2011-11-16 16:38:26 +08:00
|
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
2015-03-05 08:23:40 +08:00
|
|
|
// in v8, IfConversion depends on Thumb instruction widths
|
2015-06-09 02:50:43 +08:00
|
|
|
addPass(createThumb2SizeReductionPass([this](const Function &F) {
|
|
|
|
return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
|
|
|
|
}));
|
|
|
|
|
2016-10-25 07:23:02 +08:00
|
|
|
addPass(createIfConverter([](const MachineFunction &MF) {
|
|
|
|
return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
|
2015-06-09 02:50:43 +08:00
|
|
|
}));
|
2015-03-27 02:38:04 +08:00
|
|
|
}
|
2015-03-05 08:23:40 +08:00
|
|
|
addPass(createThumb2ITBlockPass());
|
2009-09-30 16:53:01 +08:00
|
|
|
}
|
|
|
|
|
2014-12-12 05:26:47 +08:00
|
|
|
void ARMPassConfig::addPreEmitPass() {
|
2015-03-05 08:23:40 +08:00
|
|
|
addPass(createThumb2SizeReductionPass());
|
2011-12-14 10:11:42 +08:00
|
|
|
|
2015-03-05 08:23:40 +08:00
|
|
|
// Constant island pass work on unbundled instructions.
|
2016-10-25 07:23:02 +08:00
|
|
|
addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
|
|
|
|
return MF.getSubtarget<ARMSubtarget>().isThumb2();
|
2015-06-09 02:50:43 +08:00
|
|
|
}));
|
2009-07-10 09:54:42 +08:00
|
|
|
|
2015-05-21 05:40:38 +08:00
|
|
|
// Don't optimize barriers at -O0.
|
|
|
|
if (getOptLevel() != CodeGenOpt::None)
|
|
|
|
addPass(createARMOptimizeBarriersPass());
|
|
|
|
|
2012-07-03 03:48:31 +08:00
|
|
|
addPass(createARMConstantIslandPass());
|
2006-09-19 23:49:25 +08:00
|
|
|
}
|