2011-12-13 05:14:40 +08:00
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//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is populated based on the following specs:
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// Hexagon V4 Architecture Extensions
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// Application-Level Specification
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// 80-V9418-12 Rev. A
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// June 15, 2010
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2015-02-04 03:15:11 +08:00
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// Vector reduce multiply word by signed half (32x16)
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//Rdd=vrmpyweh(Rss,Rtt)[:<<1]
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def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
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def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
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//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
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def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
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def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
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//Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
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def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
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def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
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//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
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def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
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def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
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// Vector multiply halfwords, signed by unsigned
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// Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
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def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
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def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
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// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
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def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>;
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def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>;
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// Vector polynomial multiply halfwords
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// Rdd=vpmpyh(Rs,Rt)
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def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>;
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// Rxx[^]=vpmpyh(Rs,Rt)
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def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>;
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2015-01-29 03:16:17 +08:00
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// Polynomial multiply words
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// Rdd=pmpyw(Rs,Rt)
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def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
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// Rxx^=pmpyw(Rs,Rt)
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def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
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//Rxx^=asr(Rss,Rt)
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def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
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//Rxx^=asl(Rss,Rt)
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def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
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//Rxx^=lsr(Rss,Rt)
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def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
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//Rxx^=lsl(Rss,Rt)
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def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
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// Multiply and use upper result
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def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
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def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
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def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
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def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
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def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
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2015-02-04 02:01:45 +08:00
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// Vector reduce add unsigned halfwords
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def : Pat <(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2),
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(M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>;
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2015-01-29 02:06:23 +08:00
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def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
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def: T_P_pat <S2_ct0p, int_hexagon_S2_ct0p>;
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def: T_P_pat <S2_ct1p, int_hexagon_S2_ct1p>;
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def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
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def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
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def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
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2015-01-30 00:08:43 +08:00
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def : T_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>;
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def : T_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>;
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def : T_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>;
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def : T_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>;
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def : T_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>;
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def : T_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>;
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def : T_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>;
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def : T_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>;
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def : T_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>;
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def : T_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>;
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def : T_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>;
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def : T_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>;
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2015-01-29 03:39:09 +08:00
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def : T_RP_pat <A4_boundscheck, int_hexagon_A4_boundscheck>;
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def : T_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>;
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2015-01-29 03:16:17 +08:00
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def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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(M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
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def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
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def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
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def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
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// Multiply 32x32 and use upper result
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def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
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def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
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2015-02-04 02:16:28 +08:00
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// Complex multiply 32x16
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def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>;
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def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>;
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def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>;
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def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>;
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2015-01-29 03:39:09 +08:00
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def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
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def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>;
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2015-02-04 02:16:28 +08:00
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// Complex add/sub halfwords/words
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def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>;
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def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>;
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def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>;
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def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>;
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def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>;
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def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>;
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2015-01-29 02:06:23 +08:00
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// Extract bitfield
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def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
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def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
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def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
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def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
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2015-02-04 02:01:45 +08:00
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// Vector conditional negate
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// Rdd=vcnegh(Rss,Rt)
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def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>;
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2015-01-29 01:37:59 +08:00
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// Shift an immediate left by register amount
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def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
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2015-02-04 02:01:45 +08:00
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// Vector reduce maximum halfwords
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def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>;
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def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>;
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// Vector reduce maximum words
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def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>;
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def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>;
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// Vector reduce minimum halfwords
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def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>;
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def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>;
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// Vector reduce minimum words
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def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>;
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def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>;
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2015-02-04 02:16:28 +08:00
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// Rotate and reduce bytes
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def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
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u2ImmPred:$src3),
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(S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2ImmPred:$src3)>;
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// Rotate and reduce bytes with accumulation
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// Rxx+=vrcrotate(Rss,Rt,#u2)
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def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
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IntRegs:$src3, u2ImmPred:$src4),
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(S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
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IntRegs:$src3, u2ImmPred:$src4)>;
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2015-02-04 02:01:45 +08:00
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// Vector conditional negate
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def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>;
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2015-01-29 03:39:09 +08:00
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// Logical xor with xor accumulation
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def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
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2015-02-04 02:01:45 +08:00
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// ALU64 - Vector min/max byte
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def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>;
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def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>;
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2015-01-29 01:37:59 +08:00
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// Shift and add/sub/and/or
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def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
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def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
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def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
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def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
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def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
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def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>;
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def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
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def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
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2011-12-13 05:14:40 +08:00
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2015-01-29 02:06:23 +08:00
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// Split bitfield
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def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
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def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
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def: T_RR_pat<S4_parity, int_hexagon_S4_parity>;
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def: T_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
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def: T_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
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def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>;
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def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
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def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
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2015-01-29 03:39:09 +08:00
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/********************************************************************
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* ALU32/ALU *
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*********************************************************************/
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// ALU32 / ALU / Logical Operations.
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def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
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def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
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/********************************************************************
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* ALU32/PERM *
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*********************************************************************/
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// Combine Words Into Doublewords.
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def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s8ExtPred>;
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def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
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/********************************************************************
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* ALU32/PRED *
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*********************************************************************/
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2011-12-13 05:14:40 +08:00
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2015-01-30 00:55:37 +08:00
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// Compare
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def : T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s10ExtPred>;
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def : T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s10ExtPred>;
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def : T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u9ExtPred>;
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2015-01-29 03:39:09 +08:00
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def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>;
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def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
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2011-12-13 05:14:40 +08:00
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2015-01-29 03:39:09 +08:00
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def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>;
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def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
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2011-12-13 05:14:40 +08:00
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2015-01-30 00:55:37 +08:00
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/********************************************************************
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* CR *
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*********************************************************************/
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// CR / Logical Operations On Predicates.
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class qi_CRInst_qiqiqi_pat<Intrinsic IntID, InstHexagon Inst> :
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Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt, IntRegs:$Ru)),
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(i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs),
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(C2_tfrrp IntRegs:$Rt),
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(C2_tfrrp IntRegs:$Ru))))>;
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def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_and, C4_and_and>;
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def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_andn, C4_and_andn>;
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def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_or, C4_and_or>;
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def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_orn, C4_and_orn>;
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def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_and, C4_or_and>;
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def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_andn, C4_or_andn>;
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def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_or, C4_or_or>;
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def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_orn, C4_or_orn>;
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2015-01-29 03:39:09 +08:00
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/********************************************************************
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* XTYPE/ALU *
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*********************************************************************/
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// Add And Accumulate.
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def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
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def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
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// XTYPE / ALU / Logical-logical Words.
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def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>;
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def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>;
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def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>;
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def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>;
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def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>;
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def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>;
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def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>;
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def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>;
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def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>;
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def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
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def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
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def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
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def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>;
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def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
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// Modulo wrap.
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def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
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// Arithmetic/Convergent round
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// Rd=[cround|round](Rs,Rt)[:sat]
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// Rd=[cround|round](Rs,#u5)[:sat]
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def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
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def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
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def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
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def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
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def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
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def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
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def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
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