maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Thumb/thumb-memcpy-ldm-stm.ll

37 lines
1.2 KiB
LLVM
Raw Normal View History

Thumb1 load/store optimizer: Improve code to materialize new base register. There are two add-immediate instructions in Thumb1: tADDi8 and tADDi3. Only the latter supports using different source and destination registers, so whenever we materialize a new base register (at a certain offset) we'd do so by moving the base register value to the new register and then adding in place. This patch changes the code to use a single tADDi3 if the offset is small enough to fit in 3 bits. Differential Revision: http://reviews.llvm.org/D5006 llvm-svn: 216193
2014-08-22 01:11:03 +08:00
; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | FileCheck %s
Re-enable inline memcpy expansion for Thumb1. Patch by Moritz Roth! llvm-svn: 208994
2014-05-16 22:24:22 +08:00
@d = external global [64 x i32]
@s = external global [64 x i32]
; Function Attrs: nounwind
define void @t1() #0 {
entry:
Check-label a bit more specific Sometimes, the .file could be reordered and it'd identify the ldr in the filename as a bad match. llvm-svn: 217037
2014-09-03 21:32:08 +08:00
; CHECK-LABEL: t1:
[Thumb] Make load/store optimizer less conservative. If it's safe to clobber the condition flags, we can do a few extra things: it's then possible to reset the base register writeback using a SUBS, so we can try to merge even if the base register isn't dead after the merged instruction. This is effectively a (heavily bug-fixed) rewrite of r208992. llvm-svn: 218386
2014-09-25 00:35:50 +08:00
; CHECK: ldr r[[LB:[0-9]]],
; CHECK-NEXT: ldm r[[LB]]!,
; CHECK-NEXT: ldr r[[SB:[0-9]]],
; CHECK-NEXT: stm r[[SB]]!,
; CHECK-NEXT: ldrb {{.*}}, [r[[LB]]]
; CHECK-NEXT: strb {{.*}}, [r[[SB]]]
ARM: Fix and re-enable load/store optimizer for Thumb1. In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. llvm-svn: 215729
2014-08-16 01:00:30 +08:00
tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([64 x i32]* @s to i8*), i8* bitcast ([64 x i32]* @d to i8*), i32 17, i32 4, i1 false)
Re-enable inline memcpy expansion for Thumb1. Patch by Moritz Roth! llvm-svn: 208994
2014-05-16 22:24:22 +08:00
ret void
}
; Function Attrs: nounwind
define void @t2() #0 {
entry:
ARM: Fix and re-enable load/store optimizer for Thumb1. In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. llvm-svn: 215729
2014-08-16 01:00:30 +08:00
; CHECK-LABEL: t2:
[Thumb] Make load/store optimizer less conservative. If it's safe to clobber the condition flags, we can do a few extra things: it's then possible to reset the base register writeback using a SUBS, so we can try to merge even if the base register isn't dead after the merged instruction. This is effectively a (heavily bug-fixed) rewrite of r208992. llvm-svn: 218386
2014-09-25 00:35:50 +08:00
; CHECK: ldr r[[LB:[0-9]]],
; CHECK-NEXT: ldm r[[LB]]!,
; CHECK-NEXT: ldr r[[SB:[0-9]]],
; CHECK-NEXT: stm r[[SB]]!,
; CHECK-NEXT: ldrh {{.*}}, [r[[LB]]]
; CHECK-NEXT: ldrb {{.*}}, [r[[LB]], #2]
; CHECK-NEXT: strb {{.*}}, [r[[SB]], #2]
; CHECK-NEXT: strh {{.*}}, [r[[SB]]]
Re-enable inline memcpy expansion for Thumb1. Patch by Moritz Roth! llvm-svn: 208994
2014-05-16 22:24:22 +08:00
tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([64 x i32]* @s to i8*), i8* bitcast ([64 x i32]* @d to i8*), i32 15, i32 4, i1 false)
ret void
}
; Function Attrs: nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1