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llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c

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[ARM][MVE][Intrinsics] Add MVE VMUL intrinsics. Remove annoying "t1" from VMUL* instructions. Add unit tests. Summary: Add MVE VMUL intrinsics. Remove annoying "t1" from VMUL* instructions. Add unit tests. Reviewers: simon_tatham, ostannard, dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70546
2019-11-25 22:10:59 +08:00
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
[ARM] Replace arm vendor with none. NFC
2020-04-22 23:33:11 +08:00
// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s
// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s
[ARM][MVE][Intrinsics] Add MVE VMUL intrinsics. Remove annoying "t1" from VMUL* instructions. Add unit tests. Summary: Add MVE VMUL intrinsics. Remove annoying "t1" from VMUL* instructions. Add unit tests. Reviewers: simon_tatham, ostannard, dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70546
2019-11-25 22:10:59 +08:00
#include <arm_mve.h>
// CHECK-LABEL: @test_vmulq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = mul <16 x i8> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
uint8x16_t test_vmulq_u8(uint8x16_t a, uint8x16_t b)
{
#ifdef POLYMORPHIC
return vmulq(a, b);
#else /* POLYMORPHIC */
return vmulq_u8(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = mul <8 x i16> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vmulq_s16(int16x8_t a, int16x8_t b)
{
#ifdef POLYMORPHIC
return vmulq(a, b);
#else /* POLYMORPHIC */
return vmulq_s16(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = mul <4 x i32> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
uint32x4_t test_vmulq_u32(uint32x4_t a, uint32x4_t b)
{
#ifdef POLYMORPHIC
return vmulq(a, b);
#else /* POLYMORPHIC */
return vmulq_u32(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = fmul <4 x float> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <4 x float> [[TMP0]]
//
float32x4_t test_vmulq_f32(float32x4_t a, float32x4_t b)
{
#ifdef POLYMORPHIC
return vmulq(a, b);
#else /* POLYMORPHIC */
return vmulq_f32(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_s8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
int8x16_t test_vmulq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vmulq_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vmulq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vmulq_m_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vmulq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vmulq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]], <8 x half> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x half> [[TMP2]]
//
float16x8_t test_vmulq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vmulq_m_f16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
[ARM][MVE][Intrinsics] Add *_x() variants of my *_m() intrinsics. Summary: Better use of multiclass is used, and this helped find some existing bugs in the predicated VMULL* intrinsics, which are now fixed. The refactored VMULL[TB]Q_(INT|POLY)_M() intrinsics were discovered to have an argument ("inactive") with incorrect type, and this required a fix that is included in this whole patch. The argument "inactive" should have been the same width (per vector element) as the return type of the intrinsic, but was not in the case where the return type was double the element width of the input types. To assist in testing the multiclassing , and to thwart further gremlins, the unit tests are improved in scope. The *.ll tests are all generated by a small bit of throw-away scripting from the corresponding *.c tests, and as such the diffs are large and nasty. Look at the file rather than the diff. Reviewers: dmgreen, miyuki, ostannard, simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71421
2019-12-12 01:53:12 +08:00
// CHECK-LABEL: @test_vmulq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vmulq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vmulq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vmulq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-LABEL: @test_vmulq_x_f32(
[ARM][MVE][Intrinsics] Add *_x() variants of my *_m() intrinsics. Summary: Better use of multiclass is used, and this helped find some existing bugs in the predicated VMULL* intrinsics, which are now fixed. The refactored VMULL[TB]Q_(INT|POLY)_M() intrinsics were discovered to have an argument ("inactive") with incorrect type, and this required a fix that is included in this whole patch. The argument "inactive" should have been the same width (per vector element) as the return type of the intrinsic, but was not in the case where the return type was double the element width of the input types. To assist in testing the multiclassing , and to thwart further gremlins, the unit tests are improved in scope. The *.ll tests are all generated by a small bit of throw-away scripting from the corresponding *.c tests, and as such the diffs are large and nasty. Look at the file rather than the diff. Reviewers: dmgreen, miyuki, ostannard, simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71421
2019-12-12 01:53:12 +08:00
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> undef)
// CHECK-NEXT: ret <4 x float> [[TMP2]]
//
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
float32x4_t test_vmulq_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
[ARM][MVE][Intrinsics] Add *_x() variants of my *_m() intrinsics. Summary: Better use of multiclass is used, and this helped find some existing bugs in the predicated VMULL* intrinsics, which are now fixed. The refactored VMULL[TB]Q_(INT|POLY)_M() intrinsics were discovered to have an argument ("inactive") with incorrect type, and this required a fix that is included in this whole patch. The argument "inactive" should have been the same width (per vector element) as the return type of the intrinsic, but was not in the case where the return type was double the element width of the input types. To assist in testing the multiclassing , and to thwart further gremlins, the unit tests are improved in scope. The *.ll tests are all generated by a small bit of throw-away scripting from the corresponding *.c tests, and as such the diffs are large and nasty. Look at the file rather than the diff. Reviewers: dmgreen, miyuki, ostannard, simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71421
2019-12-12 01:53:12 +08:00
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-LABEL: @test_vmulq_n_u8(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <16 x i8> [[DOTSPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = mul <16 x i8> [[A:%.*]], [[DOTSPLAT]]
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
uint8x16_t test_vmulq_n_u8(uint8x16_t a, uint8_t b)
{
#ifdef POLYMORPHIC
return vmulq(a, b);
#else /* POLYMORPHIC */
return vmulq_n_u8(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_n_s16(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x i16> [[DOTSPLATINSERT]], <8 x i16> poison, <8 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = mul <8 x i16> [[A:%.*]], [[DOTSPLAT]]
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vmulq_n_s16(int16x8_t a, int16_t b)
{
#ifdef POLYMORPHIC
return vmulq(a, b);
#else /* POLYMORPHIC */
return vmulq_n_s16(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_n_u32(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = mul <4 x i32> [[A:%.*]], [[DOTSPLAT]]
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
uint32x4_t test_vmulq_n_u32(uint32x4_t a, uint32_t b)
{
#ifdef POLYMORPHIC
return vmulq(a, b);
#else /* POLYMORPHIC */
return vmulq_n_u32(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_n_f32(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x float> [[DOTSPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = fmul <4 x float> [[A:%.*]], [[DOTSPLAT]]
// CHECK-NEXT: ret <4 x float> [[TMP0]]
//
float32x4_t test_vmulq_n_f32(float32x4_t a, float32_t b)
{
#ifdef POLYMORPHIC
return vmulq(a, b);
#else /* POLYMORPHIC */
return vmulq_n_f32(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_n_s8(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <16 x i8> [[DOTSPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[DOTSPLAT]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
int8x16_t test_vmulq_m_n_s8(int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vmulq_m_n_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_n_u16(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x i16> [[DOTSPLATINSERT]], <8 x i16> poison, <8 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[DOTSPLAT]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vmulq_m_n_u16(uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vmulq_m_n_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_n_s32(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[DOTSPLAT]], <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vmulq_m_n_s32(int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vmulq_m_n_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_n_f16(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x half> poison, half [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x half> [[DOTSPLATINSERT]], <8 x half> poison, <8 x i32> zeroinitializer
[ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen Summary: On the process of moving the argument lowering handling for half-precision floating point arguments and returns to the backend, this patch removes the code that was responsible for handling the coercion of those arguments in Clang's Codegen. Reviewers: rjmccall, chill, ostannard, dnsampaio Reviewed By: ostannard Subscribers: stuij, kristof.beyls, dmgreen, danielkiss, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D81451
2020-06-09 16:52:01 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[DOTSPLAT]], <8 x i1> [[TMP1]], <8 x half> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x half> [[TMP2]]
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
//
float16x8_t test_vmulq_m_n_f16(float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vmulq_m_n_f16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_x_n_u8(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <16 x i8> [[DOTSPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[DOTSPLAT]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vmulq_x_n_u8(uint8x16_t a, uint8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_n_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_x_n_s16(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x i16> poison, i16 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x i16> [[DOTSPLATINSERT]], <8 x i16> poison, <8 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[DOTSPLAT]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vmulq_x_n_s16(int16x8_t a, int16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_n_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_x_n_u32(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[DOTSPLAT]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vmulq_x_n_u32(uint32x4_t a, uint32_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_n_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_x_n_f32(
// CHECK-NEXT: entry:
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D93793
2020-12-24 08:33:58 +08:00
// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x float> [[DOTSPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
[ARM,MVE] Add vector-scalar intrinsics Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode). Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74620
2020-02-18 01:47:05 +08:00
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[DOTSPLAT]], <4 x i1> [[TMP1]], <4 x float> undef)
// CHECK-NEXT: ret <4 x float> [[TMP2]]
//
float32x4_t test_vmulq_x_n_f32(float32x4_t a, float32_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_n_f32(a, b, p);
#endif /* POLYMORPHIC */
}