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llvm-project/llvm/test/CodeGen/X86/tailcallstack64.ll

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Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 07:20:51 +08:00
; RUN: llc < %s -tailcallopt -mcpu=generic -mtriple=x86_64-linux -post-RA-scheduler=true | FileCheck %s
; RUN: llc < %s -tailcallopt -mcpu=generic -mtriple=x86_64-win32 -post-RA-scheduler=true | FileCheck %s
Target/X86: Tweak win64's tailcall. llvm-svn: 124272
2011-01-26 10:04:09 +08:00
; FIXME: Redundant unused stack allocation could be eliminated.
Fix some tests that depend on register allocation. llvm-svn: 132602
2011-06-04 06:45:21 +08:00
; CHECK: subq ${{24|72|80}}, %rsp
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478
2008-04-30 17:19:47 +08:00
; Check that lowered arguments on the stack do not overwrite each other.
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
; Add %in1 %p1 to a different temporary register (%eax).
Fix register-dependent X86 tests. llvm-svn: 128867
2011-04-05 08:32:44 +08:00
; CHECK: movl [[A1:32|144]](%rsp), [[R1:%e..]]
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
; Move param %in1 to temp register (%r10d).
Fix register-dependent X86 tests. llvm-svn: 128867
2011-04-05 08:32:44 +08:00
; CHECK: movl [[A2:40|152]](%rsp), [[R2:%[a-z0-9]+]]
Teach two-address lowering how to unfold a load to open up commuting opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. llvm-svn: 106493
2010-06-22 06:17:20 +08:00
; Add %in1 %p1 to a different temporary register (%eax).
Fix register-dependent X86 tests. llvm-svn: 128867
2011-04-05 08:32:44 +08:00
; CHECK: addl {{%edi|%ecx}}, [[R1]]
Update test. llvm-svn: 87049
2009-11-13 09:01:58 +08:00
; Move param %in2 to stack.
Fix register-dependent X86 tests. llvm-svn: 128867
2011-04-05 08:32:44 +08:00
; CHECK: movl [[R2]], [[A1]](%rsp)
Revert r87049, which was the workaround for the regression triggered by the recent FixedStackPseudoSourceValue-related changes, now that the specific bug that affected it is fixed, in r88954. llvm-svn: 88997
2009-11-17 07:43:42 +08:00
; Move result of addition to stack.
Fix register-dependent X86 tests. llvm-svn: 128867
2011-04-05 08:32:44 +08:00
; CHECK: movl [[R1]], [[A2]](%rsp)
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
2009-08-05 09:29:28 +08:00
; Eventually, do a TAILCALL
; CHECK: TAILCALL
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478
2008-04-30 17:19:47 +08:00
Turn on post-alloc scheduling for x86. llvm-svn: 84431
2009-10-19 03:57:27 +08:00
declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478
2008-04-30 17:19:47 +08:00
Turn on post-alloc scheduling for x86. llvm-svn: 84431
2009-10-19 03:57:27 +08:00
define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478
2008-04-30 17:19:47 +08:00
entry:
%tmp = add i32 %in1, %p1
Fix Bug 4278: X86-64 with -tailcallopt calling convention out of sync with regular cc. The only difference between the tail call cc and the normal cc was that one parameter register - R9 - was reserved for calling functions through a function pointer. After time the tail call cc has gotten out of sync with the regular cc. We can use R11 which is also caller saved but not used as parameter register for potential function pointers and remove the special tail call cc on x86-64. llvm-svn: 73233
2009-06-13 00:26:57 +08:00
%retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
Really commit the test checking the argument lowering behaviour on x86-64 :). llvm-svn: 50478
2008-04-30 17:19:47 +08:00
ret i32 %retval
}