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llvm-project/llvm/test/CodeGen/X86/lea.ll

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Relax expressions and add explicit triplets -linux and -win32. llvm-svn: 126205
2011-02-22 15:20:26 +08:00
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
filecheckize some tests llvm-svn: 81259
2009-09-09 06:38:46 +08:00
define i32 @test1(i32 %x) nounwind {
%tmp1 = shl i32 %x, 3
%tmp2 = add i32 %tmp1, 7
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
ret i32 %tmp2
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test1:
X86: Stop LEA64_32r doing unspeakable things to its arguments. Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. llvm-svn: 183693
2013-06-11 04:43:49 +08:00
; CHECK: leal 7(,%r[[A0:di|cx]],8), %eax
Add a lea instruction selection test case. llvm-svn: 28549
2006-05-30 14:53:55 +08:00
}
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
filecheckize some tests llvm-svn: 81259
2009-09-09 06:38:46 +08:00
; ISel the add of -4 with a neg and use an lea for the rest of the
; arithemtic.
define i32 @test2(i32 %x_offs) nounwind readnone {
entry:
%t0 = icmp sgt i32 %x_offs, 4
br i1 %t0, label %bb.nph, label %bb2
bb.nph:
%tmp = add i32 %x_offs, -5
%tmp6 = lshr i32 %tmp, 2
%tmp7 = mul i32 %tmp6, -4
%tmp8 = add i32 %tmp7, %x_offs
%tmp9 = add i32 %tmp8, -4
ret i32 %tmp9
bb2:
ret i32 %x_offs
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test2:
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; CHECK: leal -5(%r[[A0:..]]), %eax
change selectiondag to add the sign extended versions of immediate operands to instructions instead of zero extended ones. This makes the asmprinter print signed values more consistently. This apparently only really affects the X86 backend. llvm-svn: 81265
2009-09-09 07:05:44 +08:00
; CHECK: andl $-4, %eax
filecheckize some tests llvm-svn: 81259
2009-09-09 06:38:46 +08:00
; CHECK: negl %eax
X86: Stop LEA64_32r doing unspeakable things to its arguments. Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. llvm-svn: 183693
2013-06-11 04:43:49 +08:00
; CHECK: leal -4(%r[[A0]],%rax), %eax
filecheckize some tests llvm-svn: 81259
2009-09-09 06:38:46 +08:00
}