llvm-project/llvm/test/CodeGen/X86/coalescer-remat.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xor | count 3

@val = internal global i64 0
@"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00"

define i32 @main() nounwind {
entry:
  %0 = cmpxchg i64* @val, i64 0, i64 1 monotonic monotonic
  %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind
  ret i32 0
}

declare i32 @printf(i8*, ...) nounwind
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290 2009-09-09 07:54:48 +08:00			`; RUN: llc < %s -mtriple=x86_64-apple-darwin \| grep xor \| count 3`
Re-materalized definition instructions may be dead. Whack them. llvm-svn: 56352 2008-09-20 01:38:47 +08:00
Convert a bunch more tests over to the new atomic instructions. llvm-svn: 140582 2011-09-27 07:15:09 +08:00			`@val = internal global i64 0`
			`@"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00"`
Re-materalized definition instructions may be dead. Whack them. llvm-svn: 56352 2008-09-20 01:38:47 +08:00
			`define i32 @main() nounwind {`
			`entry:`
IR: add a second ordering operand to cmpxhg for failure The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559 2014-03-11 18:48:52 +08:00			`%0 = cmpxchg i64* @val, i64 0, i64 1 monotonic monotonic`
Convert a bunch more tests over to the new atomic instructions. llvm-svn: 140582 2011-09-27 07:15:09 +08:00			`%1 = tail call i32 (i8, ...) @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind`
			`ret i32 0`
Re-materalized definition instructions may be dead. Whack them. llvm-svn: 56352 2008-09-20 01:38:47 +08:00			`}`

			`declare i32 @printf(i8*, ...) nounwind`