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llvm-project/llvm/test/CodeGen/Hexagon/swp-vmult.ll

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Disable flaky tests till they get fixed. llvm-svn: 329763
2018-04-11 06:07:29 +08:00
; REQUIRES: to-be-fixed
MachinePipeliner pass that implements Swing Modulo Scheduling Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
2016-07-30 00:44:44 +08:00
; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s | FileCheck %s
; Multiply and accumulate
[Hexagon] Replace instruction definitions with auto-generated ones llvm-svn: 294753
2017-02-10 23:33:13 +08:00
; CHECK: mpyi([[REG0:r([0-9]+)]],[[REG1:r([0-9]+)]])
[Hexagon] Give priority to post-incremementing memory accesses in LSR llvm-svn: 328506
2018-03-26 23:32:03 +08:00
; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}}++#4)
; CHECK-NEXT: [[REG0]] = memw(r{{[0-9]+}}++#4)
MachinePipeliner pass that implements Swing Modulo Scheduling Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
2016-07-30 00:44:44 +08:00
; CHECK-NEXT: endloop0
[Hexagon] Give priority to post-incremementing memory accesses in LSR llvm-svn: 328506
2018-03-26 23:32:03 +08:00
define i32 @f0(i32* %a0, i32* %a1, i32 %a2) {
b0:
br label %b1
MachinePipeliner pass that implements Swing Modulo Scheduling Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
2016-07-30 00:44:44 +08:00
[Hexagon] Give priority to post-incremementing memory accesses in LSR llvm-svn: 328506
2018-03-26 23:32:03 +08:00
b1: ; preds = %b1, %b0
%v0 = phi i32 [ 0, %b0 ], [ %v7, %b1 ]
%v1 = phi i32* [ %a0, %b0 ], [ %v10, %b1 ]
%v2 = phi i32* [ %a1, %b0 ], [ %v11, %b1 ]
%v3 = phi i32 [ 0, %b0 ], [ %v8, %b1 ]
%v4 = load i32, i32* %v1, align 4
%v5 = load i32, i32* %v2, align 4
%v6 = mul nsw i32 %v5, %v4
%v7 = add nsw i32 %v6, %v0
%v8 = add nsw i32 %v3, 1
%v9 = icmp eq i32 %v8, 10000
%v10 = getelementptr i32, i32* %v1, i32 1
%v11 = getelementptr i32, i32* %v2, i32 1
br i1 %v9, label %b2, label %b1
MachinePipeliner pass that implements Swing Modulo Scheduling Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
2016-07-30 00:44:44 +08:00
[Hexagon] Give priority to post-incremementing memory accesses in LSR llvm-svn: 328506
2018-03-26 23:32:03 +08:00
b2: ; preds = %b1
ret i32 %v7
MachinePipeliner pass that implements Swing Modulo Scheduling Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
2016-07-30 00:44:44 +08:00
}