forked from OSchip/llvm-project
200 lines
7.7 KiB
LLVM
200 lines
7.7 KiB
LLVM
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; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; Test that register scvenging does not assert because of wrong
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; bits being set for Kill and Def bit vectors in replaceSuperBySubRegs
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%s.0 = type { i32, i32*, [0 x i32], [0 x i32], [1 x i32] }
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%s.1 = type { %s.2, %s.4, %s.5 }
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%s.2 = type { %s.3 }
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%s.3 = type { i32 }
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%s.4 = type { i32 }
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%s.5 = type { [0 x i32], [0 x i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)*] }
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@g0 = common global i32 0, align 4
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@g1 = common global %s.0 zeroinitializer, align 4
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@g2 = common global i32 0, align 4
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@g3 = common global i32 0, align 4
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@g4 = common global i32* null, align 4
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@g5 = common global i32 0, align 4
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@g6 = common global i32 0, align 4
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; Function Attrs: nounwind
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define i32 @f0(%s.1* nocapture readonly %a0) #0 {
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b0:
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%v0 = alloca [0 x i32], align 4
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%v1 = load i32, i32* @g0, align 4, !tbaa !0
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%v2 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 0, i32 0, i32 0
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%v3 = load i32, i32* %v2, align 4, !tbaa !0
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%v4 = load i32*, i32** getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 1), align 4, !tbaa !4
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%v5 = load i32, i32* @g2, align 4, !tbaa !0
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%v6 = sub i32 0, %v5
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%v7 = getelementptr inbounds i32, i32* %v4, i32 %v6
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%v8 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 1, i32 0
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%v9 = load i32, i32* %v8, align 4, !tbaa !0
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switch i32 %v9, label %b17 [
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i32 0, label %b1
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i32 1, label %b2
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]
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b1: ; preds = %b0
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store i32 0, i32* @g3, align 4, !tbaa !0
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br label %b2
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b2: ; preds = %b1, %b0
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%v10 = icmp eq i32 %v1, 0
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%v11 = icmp sgt i32 %v3, 0
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%v12 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 0
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%v13 = sdiv i32 %v3, 2
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%v14 = add i32 %v13, -1
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%v15 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 1
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%v16 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 2
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%v17 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 2, i32 1, i32 %v1
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%v18 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 2, i32 1, i32 0
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%v19 = sub i32 1, %v5
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%v20 = getelementptr inbounds i32, i32* %v4, i32 %v19
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%v21 = sdiv i32 %v3, 4
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%v22 = icmp slt i32 %v3, -3
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%v23 = add i32 %v3, -1
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%v24 = lshr i32 %v23, 2
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%v25 = mul i32 %v24, 4
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%v26 = add i32 %v25, 4
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%v27 = add i32 %v13, -2
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%v28 = icmp slt i32 %v26, 0
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%v29 = add i32 %v21, 1
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%v30 = select i1 %v22, i32 1, i32 %v29
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br label %b4
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b3: ; preds = %b16
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store i32 %v30, i32* @g3, align 4, !tbaa !0
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br label %b4
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b4: ; preds = %b13, %b3, %b2
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%v31 = phi i32 [ undef, %b2 ], [ %v87, %b3 ], [ %v87, %b13 ]
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%v32 = phi i32 [ undef, %b2 ], [ %v86, %b3 ], [ %v86, %b13 ]
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%v33 = phi i32 [ undef, %b2 ], [ %v35, %b3 ], [ %v35, %b13 ]
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%v34 = phi i32 [ undef, %b2 ], [ %v89, %b3 ], [ %v89, %b13 ]
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%v35 = phi i32 [ undef, %b2 ], [ %v94, %b3 ], [ %v65, %b13 ]
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br i1 %v10, label %b6, label %b5
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b5: ; preds = %b5, %b4
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br label %b5
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b6: ; preds = %b4
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br i1 %v11, label %b8, label %b7
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b7: ; preds = %b6
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store i32 0, i32* @g3, align 4, !tbaa !0
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br label %b11
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b8: ; preds = %b6
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store i32 %v26, i32* @g3, align 4, !tbaa !0
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br i1 %v28, label %b9, label %b11
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b9: ; preds = %b8
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%v36 = load i32*, i32** @g4, align 4, !tbaa !7
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br label %b10
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b10: ; preds = %b10, %b9
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%v37 = phi i32 [ %v26, %b9 ], [ %v45, %b10 ]
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%v38 = phi i32 [ %v34, %b9 ], [ %v44, %b10 ]
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%v39 = add nsw i32 %v37, %v33
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%v40 = shl i32 %v39, 1
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%v41 = getelementptr inbounds i32, i32* %v36, i32 %v40
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%v42 = load i32, i32* %v41, align 4, !tbaa !0
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%v43 = icmp slt i32 %v42, %v31
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%v44 = select i1 %v43, i32 0, i32 %v38
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%v45 = add nsw i32 %v37, 1
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store i32 %v45, i32* @g3, align 4, !tbaa !0
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%v46 = icmp slt i32 %v45, 0
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br i1 %v46, label %b10, label %b11
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b11: ; preds = %b10, %b8, %b7
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%v47 = phi i32 [ %v26, %b8 ], [ 0, %b7 ], [ 0, %b10 ]
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%v48 = phi i32 [ %v34, %b8 ], [ %v34, %b7 ], [ %v44, %b10 ]
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%v49 = load i32, i32* @g5, align 4, !tbaa !0
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%v50 = icmp slt i32 %v13, %v49
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%v51 = icmp slt i32 %v47, %v14
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%v52 = and i1 %v50, %v51
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br i1 %v52, label %b12, label %b13
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b12: ; preds = %b11
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%v53 = sub i32 %v27, %v47
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%v54 = lshr i32 %v53, 1
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%v55 = mul i32 %v54, 2
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%v56 = add i32 %v47, 2
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%v57 = add i32 %v56, %v55
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store i32 %v57, i32* @g3, align 4, !tbaa !0
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br label %b13
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b13: ; preds = %b12, %b11
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%v58 = shl i32 %v35, 2
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%v59 = load i32*, i32** @g4, align 4, !tbaa !7
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%v60 = getelementptr inbounds i32, i32* %v59, i32 %v58
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%v61 = load i32, i32* %v60, align 4, !tbaa !0
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%v62 = load i32, i32* %v7, align 4, !tbaa !0
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%v63 = add nsw i32 %v62, %v61
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%v64 = add nsw i32 %v63, %v32
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store i32 %v64, i32* %v15, align 4, !tbaa !0
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%v65 = add i32 %v35, -1
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%v66 = getelementptr inbounds i32, i32* %v59, i32 %v65
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%v67 = load i32, i32* %v66, align 4, !tbaa !0
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%v68 = sub i32 %v49, %v5
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%v69 = getelementptr inbounds i32, i32* %v4, i32 %v68
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%v70 = load i32, i32* %v69, align 4, !tbaa !0
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%v71 = add nsw i32 %v70, %v67
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%v72 = load i32, i32* %v16, align 4, !tbaa !0
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%v73 = add nsw i32 %v71, %v72
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store i32 %v73, i32* %v16, align 4, !tbaa !0
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%v74 = load i32, i32* @g6, align 4, !tbaa !0
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%v75 = load i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)*, i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)** %v17, align 4, !tbaa !7
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%v76 = load i32, i32* getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 4, i32 0), align 4, !tbaa !0
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%v77 = call i32 %v75(i32* getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 4, i32 0), i32* null, i32* null, i32* null, i32* null, i32 %v76, i32* null) #0
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%v78 = load i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)*, i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)** %v18, align 4, !tbaa !7
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%v79 = inttoptr i32 %v74 to i32*
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%v80 = load i32, i32* getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 4, i32 0), align 4, !tbaa !0
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%v81 = call i32 %v78(i32* getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 4, i32 0), i32* null, i32* null, i32* null, i32* %v79, i32 %v80, i32* %v12) #0
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%v82 = load i32*, i32** @g4, align 4, !tbaa !7
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%v83 = getelementptr inbounds i32, i32* %v82, i32 %v58
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%v84 = load i32, i32* %v83, align 4, !tbaa !0
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%v85 = load i32, i32* %v20, align 4, !tbaa !0
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%v86 = add nsw i32 %v85, %v84
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store i32 %v86, i32* %v15, align 4, !tbaa !0
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%v87 = load i32, i32* %v12, align 4, !tbaa !0
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%v88 = icmp eq i32 %v87, 0
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%v89 = select i1 %v88, i32 %v48, i32 1
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store i32 %v89, i32* @g5, align 4, !tbaa !0
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store i32 0, i32* @g3, align 4, !tbaa !0
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br i1 %v22, label %b4, label %b14
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b14: ; preds = %b16, %b13
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%v90 = phi i32 [ %v95, %b16 ], [ 0, %b13 ]
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%v91 = phi i32 [ %v94, %b16 ], [ %v65, %b13 ]
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br i1 %v88, label %b16, label %b15
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b15: ; preds = %b14
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%v92 = mul i32 %v90, -4
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%v93 = add nsw i32 %v92, 1
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br label %b16
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b16: ; preds = %b15, %b14
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%v94 = phi i32 [ %v93, %b15 ], [ %v91, %b14 ]
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%v95 = add nsw i32 %v90, 1
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%v96 = icmp slt i32 %v90, %v21
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br i1 %v96, label %b14, label %b3
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b17: ; preds = %b0
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ret i32 undef
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}
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attributes #0 = { nounwind }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"int", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{!5, !6, i64 4}
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!5 = !{!"", !1, i64 0, !6, i64 4, !2, i64 8, !2, i64 8, !2, i64 8}
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!6 = !{!"any pointer", !2, i64 0}
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!7 = !{!6, !6, i64 0}
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